• Journal of Power Electronics
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• v.14 no.6
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• pp.1119-1129
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• 2014

This study proposes a novel five-level three-phase hybrid-clamped converter composed of only six switches and one flying capacitor (FC) per phase. The capacitor-voltage-drift phenomenon of the converter under the classical sinusoidal pulse width modulation (SPWM) strategy is comprehensively analyzed. The average current, which flows into the FC, is a function of power factor and modulation index and does not remain at zero. Thus, a specific modulation strategy based on space vector modulation (SVM) is developed to balance the voltage of DC-link and FCs by injecting a common-mode voltage. This strategy applies the five-segment method to synthesize the voltage vector, such that switching losses are reduced while optional vector sequences are increased. The best vector sequence is then selected on the basis of the minimized cost function to suppress the divergence of the capacitor voltage. This study further proposes a startup method that charges the DC-link and FCs without any additional circuits. Simulation and experimental results verify the validity of the proposed converter, modulation strategy, and precharge method.

• ETRI Journal
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• v.30 no.4
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• pp.526-534
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• 2008

This paper presents a fully integrated 0.13 ${\mu}m$ CMOS MB-OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low-pass filter, a variable gain amplifier, a voltage-to-current converter, an I/Q up-mixer, a differential-to-single-ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 ${\mu}m$ CMOS technology. The fabricated transmitter shows a -3 dB bandwidth of 550 MHz at each sub-band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.

• Journal of the Semiconductor & Display Technology
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• v.7 no.2
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• pp.23-27
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• 2008

Recently, regulation for THD (Total Harmonic Distortion) such as IEC 61000-3-2, IEEE 519 is being reinforced about a product which directly connects to AC line in order to prevent distortion of common power source in electronic equipment and electrical machinery. In order to satisfy these regulations, conventional circuits were used two-stage structure attached power factor correction circuit at ahead of converter but this method complicate the circuit and then a number of element increases thereupon the cost of production rises. in this paper, we propose a high efficiency single-stage 300W PFC fly-back converter that improved power factor and efficiency than conventional two-stage power module.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.6
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• pp.494-501
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• 2006

In this paper, a novel energy recovery circuit for AC PDPs(Plasma Display Panels) with reduced sustain voltage is proposed to improve the performance of conventional circuits such as TERES(TEchnology of REciprocal Sustainer). In the TERES circuit, the sustain voltage is the half of general sustaining driver for AC PDPs, however, there is no energy recovery circuit. In the proposed circuit, the efficiency is heightened by installing in energy recovery circuit and the loss of switching device is reduced by performing the zero voltage switching or zero current switching. Although the energy recovery circuit is added, the number of active switching elements of the proposed circuit is the same as that of the TERES circuit. The operations of the proposed circuit are analyzed for each mode and its validity is verified by the simulations and experimentation.

• ETRI Journal
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• v.42 no.6
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.71-76
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• 2017

The electrical behavior and flexibility of the screen printed Ag circuits were investigated with infrared radiation sintering times and sintering temperatures. Electrical resistivity and radio frequency characteristics were evaluated by using the 4 point probe measurement and the network analyzer by using cascade's probe system, respectively. Electrical resistivity and radio frequency characteristics means that the direct current resistance and signal transmission properties of the printed Ag circuit. Flexibility of the screen printed Ag circuit was evaluated by measuring of electrical behavior during IPC sliding test. Failure mode of the Ag printed circuits was observed by using field emission scanning electron microscope and optical microscope. Electrical resistivity of the Ag circuits screen printed on Pl substrate was rapidly decreased with increasing sintering temperature and durations. The lowest electrical resistivity of Ag printed circuit was up to $3.8{\mu}{\Omega}{\cdot}cm$ at $250^{\circ}C$ for 45 min. The crack length arisen within the printed Ag circuit after $10{\times}10^4$ sliding numbers was 10 times longer than that of after $2.5{\times}10^4$ sliding numbers. Measured insertion loss and calculated insertion loss were in good agreements each other. Insertion loss of the printed Ag circuit was increased with increasing the number of sliding cycle.

• Journal of IKEEE
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• v.22 no.3
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• pp.842-845
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• 2018

In this paper, we propose low-power operational methods for thermal-energy-harvesting sensor circuits. Here, the amount of harvested current has been measured as low as 8uA. However the DC power consumption of the sensor circuit is known to consume much larger than 8uA. Thus, We propose the hardware-based power gating and software-based active/sleep timing control schemes, respectively, for controlling the power consumption of sensor circuit. In the hardware-based power gating scheme, if the ratio of Toff/Ton is larger than 22, the sensor can consume less than 8uA. For the software-based active/sleep control scheme, if the ratio of Tslp/Tact is larger than 3, we can suppress the current consumption below 8uA. The hardware-based and software-based schemes proposed in this paper would be helpful in various applications of energy-harvesting sensor circuits, where the power consumption is limited by an amount of harvested energy.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• Journal of IKEEE
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• v.24 no.3
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• pp.803-813
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• 2020

This paper presents a high efficiency resonant flyback converter using a single-chip microcontroller. The proposed converter primary performs the resonant switching by applying the asymmetrical pulse-width modulation (APWM) to the half-bridge power topology. And the converter secondary uses the diode flyback rectifier as its power topology and operates with the zero current switching (ZCS). Thus the proposed converter achieves high efficiency. The total structure of proposed converter is very simple because it uses a single-chip microcontroller and bootstrap circuit for its control and drive, respectively. First, this paper describes the converter operation according to each operation mode and shows its steady-state analysis. And the software control algorithm and drive circuits operating the proposed converter are explained. Then, the operation characteristics of proposed converter are shown through the experimental results of an implemented prototype based on each explanation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.345-352
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• 2017

In this paper, a unified potentiostat which can measure the current of both $O_2$-based and $H_2O_2$-based blood glucose sensors with low supply voltage of 1.0V has been designed and verified by simulations and measurements. Potentiostat is composed of low-voltage operational transconductance amplifier, cascode current mirrors and mode-selection circuits. It can measure currents of blood glucose chemical reactions occurred by $O_2$ or $H_2O_2$. The body of PMOS input differentional stage of the operational transconductance amplifier is forward-biased to reduce the threshold voltage for low supply voltage operation. Also, cascode current mirror is used to reduce current measurement error generated by channel length modulation effects. The proposed low-voltage potentiostat is designed and simulated using Cadence SPECTRE and fabricated in Magnachip 0.18um CMOS technology with chip size of $110{\mu}m{\times}60{\mu}m$. The measurement results show that consumption current is maximum $46{\mu}A$ at supply voltage of 1.0V. Using the persian potassium($K_3Fe(CN)_6$) equivalent to glucose, the operation of the fabricated potentiostat was confirmed.