• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
• /
• pp.142-144
• /
• 2006

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

• Journal of Power Electronics
• /
• 제10권1호
• /
• pp.21-26
• /
• 2010

The most important feature of the one-cycle control method is its excellent ability in line disturbance rejection. However, when it is used as a controller in dc-dc converters, it has an undesirable transient response. The voltage overshoot at the transient time, which usually exists in one-cycle controlled converters, is unwanted in many applications and it is sometimes hazardous. In this paper, it is shown that the combination of a one-cycle controller with a current mode controller, can improve the transient response and consequently the overshoot can be controlled. Therefore, the combined controller has the excellent line disturbance rejection of a one-cycle controller and the output current limiting capability of current mode controllers. Because in this scheme a one-cycle controller is the master controller, the problem of instability of current mode control, will not happen. By simulation and a practical prototype, the capability of the method is shown.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1998년도 전력전자학술대회 논문집
• /
• pp.275-278
• /
• 1998

The mathematical interpretation of a practical sampler which is useful to obtain the small signal models for the peak and average current mode controls is proposed. Due to the difficulties in applying the Shannon's sampling theorem to the analysis of sampling effects embedded in the current mode control, several different approaches have been reported. However, these approaches require the information of the inductor current in a discrete expression, which restricts the application of the reported method only to the peak current mode control. In this paper, the mathematical expressions of sampling effects on a current loop which can directly apply the Shannon's sampling theorem are newly proposed, and applied to the modeling of the peak current mode control. By the newly derived models of a practical sampler, the models in a discrete time domain and a continuous time domain are obtained. It is expected that the derived models are useful for the control loop design of power supplies. The effectiveness of the derived models are verified through the simulation and experimental results.

• Journal of Power Electronics
• /
• 제19권6호
• /
• pp.1582-1590
• /
• 2019

A new method for reducing the common-mode current generated by the voltage variations in a two-inverter air conditioner system by applying a synchronized pulse-width modulation (PWM) strategy is proposed. The PWM signals of the master-mode inverter are generated based on the reference voltage, while those of the slave-mode inverter are output in the opposite direction when the master-mode inverter changes its switching state. However, the slave-mode control results in a mismatch between the reference voltage and the actual output voltage that is modified by synchronized control operation. The proposed method is capable of reducing and controlling this voltage error by performing signal selection in the vector space of the slave-mode inverter, which mitigates the distortion of the phase current. The efficacy of this method in reducing conducted emissions has been validated both theoretically and experimentally.

• 한국산학기술학회논문지
• /
• 제10권12호
• /
• pp.3614-3621
• /
• 2009

본 논문에서는 이득 및 주파수 특성이 개선된 CMOS 저전압 전류모드 적분기가 설계되었다. 설계된 전류모드 적분기는 본 논문에서 새롭게 제안한 선형 캐스코드 회로를 기본으로 구성되었다. 제안된 전류모드 적분기는 기존의 전류미러형 전류모드 적분기의 이득(43.7dB) 및 단위이득주파수(15.2MHz) 비해서 높은 전류이득(47.8dB) 및 단위 이득 주파수(27.8MHz)의 특성을 얻을 수 있었다. 제안된 전류모드 적분기의 응용회로로써 차단주파수 7.03MHz를 갖는 5차 체비세프 저역통과 필터를 설계하였다. 설계된 모든 회로들은 1.8V-$0.18{\mu}m$ CMOS 공정파라메터로써 HSPICE를 이용하여 시뮬레이션되었다.

• 한국산학기술학회논문지
• /
• 제10권12호
• /
• pp.3638-3644
• /
• 2009

본 논문에서는 새롭게 제안한 선형 캐스코드 전류모드 적분기를 기본으로 구성된 다중채널 CMOS 저전압 전류모드 필터를 설계하였다. 제안된 전류모드 적분기는 기존의 전류미러형 전류모드 적분기 비해서 높은 전류이득 및 단위이득 주파수 특성을 얻을 수 있다. 5차 체비셰프 함수로써 구성한 필터는 신호흐름선도(SFG)기법에 의하여 능동필터로 변환되었다. 1.8V-$0.18{\mu}m$ CMOS 공정파라미터를 사용한 HSPICE 시뮬레이션 결과, 설계된 필터는 0.51MHz에서 7.03MHz대역까지의 주파수 조정범위를 가지며 Bluetooth, DECT, WCDMA의 3채널의 기저대역에서 사용할 수 있음을 확인하였다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제49권2호
• /
• pp.116-119
• /
• 2000

A hybrid SOI bipolar-mode field effect transistor (BMFET) is proposed to improve the current gain. The device characteristics are analyzed and verified numerically for BMFET mode, DMOS mode, and hybrid mode by MEDICI simulation. The proposed SOI BMFET exhibits 30 times larger current gain in hybrid-mode operation by connecting DMOS gate to the p+ gate of BMFET structure as compared with the conventional structure without sacrifice of breakdown voltage and leakage current characteristics. This is due to the DMOS-gate-induced hybrid effect that lowers the barrier of p-body and reduces the charge in p-body.

• Journal of Power Electronics
• /
• 제19권5호
• /
• pp.1142-1152
• /
• 2019

This paper presents a control method for reducing the current distortion in an indirect matrix converter (IMC) operating in boost mode under unbalanced input conditions. IMCs operating in boost mode are useful in distributed generation (DG) systems. They are connected with renewable energy systems (RESs) and the grid to transmit the power generated by the RES. However, under unbalanced voltage conditions of the RES, which is connected with the input stage of the IMC operating in boost mode, the input-output currents are distorted. In particular, the output current distortions cause a ripple of the power, which is transferred to the grid. This aggravates the reliability and stability of the DG system. Therefore, in this paper, a control method using positive/negative sequence voltages and currents is proposed for reducing the current distortion of both side in IMCs operating in boost mode. Simulation and experimental results have been presented to validate effectiveness of the proposed control method.

• ETRI Journal
• /
• 제26권4호
• /
• pp.292-296
• /
• 2004

In this paper we present a new current-mode electronically tunable universal filter using only plus-type current controlled conveyors (CCCII+s) and grounded capacitors. The proposed circuit can simultaneously realize lowpass, bandpass, and highpass filter functions - all at high impedance outputs. The realization of a notch response does not require additional active elements. The circuit enjoys an independent current control of parameters $\omega_0$ and $\omega_0/Q$. No element matching conditions are imposed. Both its active and passive sensitivities are low.

• 한국조명전기설비학회:학술대회논문집
• /
• 한국조명전기설비학회 2004년도 춘계학술대회 논문집
• /
• pp.506-510
• /
• 2004

A multi-phase interleaved buck converter is used to reduce current ripples and filter size of a power supply. This paper addresses the modelling and steady-state analysis of the multi-phase interleaved buck converter operated in discontinuous inductor current mode. The model is derived using an averaging technique in steady state. The do voltage ratio and the range of the discontinuous inductor current mode(DICM) and the continuous output current mode(COCM) are derived from the averaged state-space model. In addition, the efficiency is investigated according to the number of phase.