• Title/Summary/Keyword: current spreading layer

Search Result 35, Processing Time 0.025 seconds

Effects of Current Spreading in GaN-based Light-emitting Diodes Using ITO Spreading Pad

  • Kim, Jang Hyun;Kim, Garam;Park, Euyhwan;Kang, Dong Hoon;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.15 no.1
    • /
    • pp.114-121
    • /
    • 2015
  • In conventional LEDs, a mesa-structure is usually used and it causes the current to be overcrowded in a specific region. We propose a novel structure of GaN-based LED to overcome this problem. In order to distribute the current in an active region, a spreading pad is inserted at the p-type region in the GaN based LED device. The inserted spreading pad helps the current flow because it is more conductive than the p-type GaN layer. By performing electrical and optical simulations, the effects of the spreading pad insertion are confirmed. The results of electrical simulation show that the current spreads more uniformly and more radiative recombination is produced as well. Moreover, from the optical simulation, it is revealed that the ITO is less absorptive material than p-GaN if the condition of specific wavelength sources is satisfied. Considering all of the results, we can conclude that the luminescent power is enhanced by the spreading pad.

Optimization of 4H-SiC Vertical MOSFET by Current Spreading Layer and Doping Level of Epilayer (Current Spreading Layer와 에피 영역 도핑 농도에 따른 4H-SiC Vertical MOSFET 항복 전압 최적화)

  • Ahn, Jung-Joon;Moon, Kyoung-Sook;Koo, Sang-Mo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.23 no.10
    • /
    • pp.767-770
    • /
    • 2010
  • In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state ($5{\times}10^{17}cm^{-3}$). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from $1{\times}10^{16}cm^{-3}$ to $1{\times}10^{17}cm^{-3}$, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

Design and Optimization of 4.5 kV 4H-SiC MOSFET with Current Spreading Layer (Current Spreading Layer를 도입한 4.5 kV 4H-SiC MOSFET의 설계 및 최적화)

  • Young-Hun, Cho;Hyung-Jin, Lee;Hee-Jae, Lee;Geon-Hee, Lee;Sang-Mo, Koo
    • Journal of IKEEE
    • /
    • v.26 no.4
    • /
    • pp.728-735
    • /
    • 2022
  • In this work, we investigated a high-voltage (~4.5 kV) 4H-SiC power DMOSFET with modifications of current spreading layer (CSL), which was introduced below the p-well region for low on-resistance. These include the following: 1) a thickness of CSL (TCSL) from 0 um to 0.9 um; 2) a doping concentration of CSL (NCSL) from 1×1016 cm-3 to 5×1016 cm-3. The design is optimized using TCAD 2D-simulation, and we found that CSL helps to reduce specific on-resistance but also breakdown voltage. The resulting structures exhibit a specific on-resistance (Ron,sp) of 59.61 mΩ·cm2, a breakdown voltage (VB) of 5 kV, and a Baliga's Figure of Merit (BFOM) of 0.43 GW/cm2.

Enhanced Luminous Intensity in LEDs with Current Blocking Layer (전류 차단 층을 갖는 LED의 향상된 광세기)

  • Yoon, Seok-Beom;Kwon, Kee-Young;Choi, Ki-Seok
    • Journal of Digital Convergence
    • /
    • v.12 no.7
    • /
    • pp.291-296
    • /
    • 2014
  • Inserting a $SiO_2$ layer underneath the p-pad electrode as the current blocking layer (CBL) structure and extending p-metal finger patterns, the GaN LEDs using an indium-tin-oxide (ITO) layer show the improved light output intensity, resulting from better current spreading and reduced light loss on the surface of p-pad metal. The LEDs with an oxide layer of $100{\mu}m$-pad-width and $6{\mu}m$-finger-width have better light output intensities than those with an oxide layer of $105{\mu}m$-pad-width and $12{\mu}m$-finger-width. Using the ATLAS device simulator from Silvaco Corporation, the current density distributions on the active layer in CBL LEDs have been investigated.

Highly Transparent Indium Oxide Doped ZnO Spreading Layer for GaN Based Light Emitting Diodes

  • Lim, Jae-Hong;Park, Seong-Ju
    • Korean Journal of Materials Research
    • /
    • v.19 no.8
    • /
    • pp.443-446
    • /
    • 2009
  • This study develops a highly transparent ohmic contact scheme using indium oxide doped ZnO (IZO) as a current spreading layer for p-GaN in order to increase the optical output power of nitride-based lightemitting diodes (LEDs). IZO based contact layers of IZO, Ni/IZO, and NiO/IZO were prepared by e-beam evaporation, followed by a post-deposition annealing. The transmittances of the IZO based contact layers were in excess of 80% throughout the visible region of the spectrum. Specific contact resistances of $3.4\times10^{-4}$, $1.2\times10^{-4}$, $9.2\times0^{-5}$, and $3.6\times10^{-5}{\Omega}{\cdot}cm^2$ for IZO, Ni/Au, Ni/IZO, and NiO/IZO, respectively were obtained. The forward voltage and the optical output power of GaN LED with a NiO/IZO ohmic contact was 0.15 V lower and was increased by 38.9%, respectively, at a forward current of 20 mA compared to that of a standard GaN LED with an Ni/Au ohmic contact due to its high transparency, low contact resistance, and uniform current spreading.

A simulation study on the figure of merit optimization of a 1200V 4H-SiC DMOSFET (1200V급 4H-SiC DMOSFET 성능지수 최적화 설계 시뮬레이션)

  • Choi, Chang-Yong;Kang, Min-Suk;Bang, Wook;Kim, Sang-Chul;Kim, Nam-Kyun;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2009.06a
    • /
    • pp.63-63
    • /
    • 2009
  • In this work, we demonstrate 800V 4H-SiC power DMOSFETs with several structural alterations to observe static DC characteristics, such as a threshold voltage ($V_{TH}$) and a figure of merit ($V_B^2/R_{SP,ON}$). To optimize the static DC characteristics, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. Design parameters are optimized using 2D numerical simulations and the 4H-SiC DMOSFET structure results in high figure of merit ($V_B^2/R_{SP,ON}$>~$340MW/cm^2$) for a power MOSFET in $V_B{\sim}1200V$ range.

  • PDF

A Simulation Study on the Structural Optimization of a 800 V 4H-SiC Power DMOSFET (800 V급 4H-SiC DMOSFET 전력 소자 구조 최적화 시뮬레이션)

  • Choi, Chang-Yong;Kang, Min-Seok;Bahng, Wook;Kim, Sang-Cheol;Kim, Nam-Kyun;Koo, Sang-Mo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.22 no.8
    • /
    • pp.637-640
    • /
    • 2009
  • In this work, we demonstrate 800 V 4H-SiC power DMOSFETs with several structural alterations to obtain a low threshold voltage ($V_{TH}$) and a high figure of merit ($V_B\;^2/R_{SP,ON}$), To optimize the device performance, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. These parameters are optimized using 2D numerical simulation and the 4H-SiC DMOSFET structure results in a threshold voltage ($V_{TH}$) below $^{\sim}$3.8 V, and high figure of merit ($V_B\;^2/R_{SP,ON}$>$^{\sim}$200 $MW/cm^2$) for a power MOSFET in $V_B\;^{\sim}$800 V range.

Preliminary Study on Pre-Heating Process of Stellite21 Powder Using Electron Beam (전자빔을 이용한 Stellite21 분말 예열공정에 관한 기초 연구)

  • Lee, Ho-Jin;Song, Jae-Guk;Kim, Jin-Suk;Ahn, Dong-Gyu
    • Journal of the Korean Society for Precision Engineering
    • /
    • v.33 no.5
    • /
    • pp.419-425
    • /
    • 2016
  • A powder spreading phenomenon is one of disadvantageous characteristics of the powder bed fusion process using electron beams. The powder spreading phenomenon can be controlled using a pre-heating process of metallic powders. The aim of this paper was to investigate the preheating process of Stellite21 powder using electron beams. Powder spreading experiments were performed to examine the influence of process parameters on the spreading behaviors of Stellite21 powder. Powder heating experiments were carried to investigate the effects of the focusing current of the electron beam on the quality of the heated region. Using the results of the powder spreading and heating experiments, an appropriate combination of process parameters was obtained. The pre-heating experiment of Stellite21 was performed using the estimated combination of process parameters. The results of preheating experiments showed that the preheated Stelllite21 layer with desired characteristics can be created when the estimated combination of process parameters is applied.

Study on the Current Spreading Effect of Blue GaN/InGaN LED using 3-Dimensional Circuit Modeling (3차원의 회로 모델링을 이용한 청색 GaN/InGaN LED의 전류 확산 효과에 관한 연구)

  • Hwang, Sung-Min;Shim, Jong-In
    • Korean Journal of Optics and Photonics
    • /
    • v.18 no.2
    • /
    • pp.155-161
    • /
    • 2007
  • A new and simple method of 3-dimensional circuit modeling and analysis is proposed and verified experimentally for the first time by determining 3-dimensional current flow and 2-dimensional light distribution in blue InGaN/GaN multi-quantum well (MQW) light emitting diode (LED) devices. Circuit parameters of the LED consist of the resistance of the metallic film and epitaxial layer, and the intrinsic diode which represents the active region emitting the light. The circuit parameters are extracted from the transmission line model (TLM) and current-voltage relation. We applied the >> proposed method and extracted circuit parameters to obtain the light emission pattern in a top-surface emitting-type LED. The current spreading effect is analyzed theoretically and quantitatively with a variation of the resistance of metallic and epitaxial layers. The emitting-light distribution of the fabricated blue LED showed a good agreement with the analyzed result, which shows the dark emission intensity at the corner of the p-electrode.

A simulation study on the structural optimization of a 800V 4H-SiC Power DMOSFET (800V급 4H-SiC DMOSFET 전력 소자 구조 최적화 시뮬레이션)

  • Choi, Chang-Yong;Gang, Min-Seok;Bang, Wook;Kim, Sang-Chul;Kim, Nam-Kyun;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2009.04b
    • /
    • pp.35-36
    • /
    • 2009
  • In this work, we demonstrate 800V 4H-SiC power DMOSFETs with several structural alterations to obtain a low threshold voltage ($V_{TH}$) and a high figure of merit ($V_B^2/R_{SP,ON}$). To optimize the device performance, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. These parameters are optimized using 2D numerical simulation and the 4H-SiC DMOSFET structure results in a threshold voltage ($V_{TH}$) below ~3.8V, and high figure of merit ($V_B^2/R_{SP,ON}$>${\sim}200MW/cm^2$) for a power MOSFET in $V_B$-800V range.

  • PDF