A simulation study on the structural optimization of a 800V 4H-SiC Power DMOSFET

800V급 4H-SiC DMOSFET 전력 소자 구조 최적화 시뮬레이션

In this work, we demonstrate 800V 4H-SiC power DMOSFETs with several structural alterations to obtain a low threshold voltage ($V_{TH}$) and a high figure of merit ($V_B^2/R_{SP,ON}$). To optimize the device performance, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. These parameters are optimized using 2D numerical simulation and the 4H-SiC DMOSFET structure results in a threshold voltage ($V_{TH}$) below ~3.8V, and high figure of merit ($V_B^2/R_{SP,ON}$>${\sim}200MW/cm^2$) for a power MOSFET in $V_B$-800V range.