• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 춘계학술대회 논문집 에너지변화시스템부문
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• pp.152-155
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• 2009

In high power application, PFC(Power Factor Correction) pre-regulators are generally required. PFC pre-regulators could achieve unity power factor, reduce line input current harmonics and utilize full line power. Interleaving PFC converters could reduce input ripple current, output capacitor ripple current and inductor size. With this closed loop interleaving method, both two phase converters are working at the boundary between continuous and discontinuous mode and accurate 180 degree phase shift is achieved. Implementation of this strategy could be easily integrated to the control chip. Finally, experimental results of a two-phase interleaved boost PFC are presented to verify the discussed features.

• 전력전자학회논문지
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• 제21권3호
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• pp.260-266
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• 2016

A new method for the current ripple reduction of a three-phase interleaved bidirectional DC-DC converter is proposed. The converter used in this study operates in discontinuous mode to minimize the switching losses. All the switches are turned on at ZVS and ZCS conditions, and turned off at ZVS condition. The charging and discharging power of the battery is controlled by varying the switching frequency while maintaining the discontinuous mode operation. A 3 kW 20 kHz power converter is designed and implemented. Simulation and experimental results show the validity of the proposed method. The proposed control method can be used to reduce the battery ripple current significantly.

• 전력전자학회논문지
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• 제3권4호
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• pp.280-286
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• 1998

본 논문에서는 벡터제어방식의 인버터에 의하여 구동되는 교류전동기 제어 시스템에서 전류특정회로에서의 측정오차에 기인하는 전동기의 토크리플을 저감하는 방법을 제안한다. 2상의 전류를 측정하는 회로에서의 오프셋 전압과 전압증폭률이 서로 다를 때 전동기 출력토크에 발생되는 리플을 각각 정량적으로 분석하고, 이로부터 온라인 상태에서 실시간으로 토크리플을 제거할 수 있는 알고리즘을 제시하였다. 제안된 방식의 유용성을 확인하기 위하여 이를 영구자석형 동기전동기에 적용하였을 경우에 대하여 출력토크의 리플을 계산하고 이를 제거하는 알고리즘을 컴퓨터로 시뮬레이션하였다.

• Journal of Power Electronics
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• 제15권2호
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• pp.327-337
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• 2015

This study discusses the design of a parallel-operated DC-DC single-ended primary-inductor converter (SEPIC) for low-voltage application and current sharing with a constant output voltage. A coupled inductor is used for parallel-connected SEPIC topology. Generally, two separate inductors require different ripple currents, but a coupled inductor has the advantage of using the same ripple current. Furthermore, tightly coupled inductors require only half of the ripple current that separate inductors use. In this proposed work, tightly coupled inductors are used. These produce an output that is more efficient than that from separate inductors. Two SEPICs are also connected in parallel using the coupled inductors with a single common controller. An analog control circuit is designed to generate pulse width modulation (PWM) signals and to fulfill the closed-loop control function. A stable output current-sharing strategy is proposed in this system. An experimental setup is developed for a 18.5 V, 60 W parallel SEPIC (PSEPIC) converter, and the results are verified. Results indicate that the PSEPIC provides good response for the variation of input voltage and sudden change in load.

• Journal of Power Electronics
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• 제10권6호
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• pp.709-716
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• 2010

MDPS (motor driven power steering) systems have been widely used in vehicles due to their improved fuel efficiency and steering performance when compared to conventional hydraulic steering. However, the reduction of torque ripples and material cost are important issues. A low resolution position sensor for MDPS is one of the candidates for reducing the material costs. However, it may increases the torque ripple due to the current harmonics caused by low resolution encoder signals. In this paper, the torque ripple caused by the quantized rotor position of the low resolution encoder is analyzed. To reduce the torque ripples caused by the quantization of the encoder signals, the rotor position and the speed are estimated by measuring the frequency of the encoder signals. In addition, the compensating q-axis current is added to the current command so that the 6th order torque harmonic is attenuated. The reduction of torque ripples by applying the estimated rotor position and the compensated q-axis current is verified through experimental results.

• Journal of Power Electronics
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• 제17권3호
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• pp.590-600
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• 2017

This paper presents a ripple-free input current modified interleaved boost converter for high step-up applications. By integrating dual coupled inductors and voltage multiplier techniques, the proposed converter can reach a high step-up gain without an extremely high turn-ON period. In addition, a very small auxiliary inductor employed in series to the input dc source makes the input current ripple theoretically decreased to zero, which simplifies the design of the electromagnetic interference (EMI) filter. In addition, the voltage stresses on the semiconductor devices of the proposed converter are efficiently reduced, which makes high performance MOSFETs with low voltage rated and low resistance $r_{DS}$(ON) available to reduce the cost and conduction loss. The operating principles and steady-state analyses of the proposed converter are introduced in detail. Finally, a prototype circuit rated at 400W with a 42-50V input voltage and a 400V output voltage is built and tested to verify the effectiveness of theoretical analysis. Experimental results show that an efficiency of 95.3% can be achieved.

• 전력전자학회논문지
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• 제26권2호
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• pp.96-105
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• 2021

Large-scale power converters consist of series or parallel module combinations. In these modular converter systems, the interleaving technique can be applied to improve capacitor reliability by reducing the ripple of the I/O current in which each module operates as a phase difference. However, when applying the interleaving technique for conventional three-level boost converters, the short-circuit period of the converter can be an obstacle. Such problem is caused by the absence of a low-level inductor of the conventional three-level boost converter. To solve this problem, a three-level boost converter with a low-level inductor is proposed and analyzed to enable interleaved operation. In the proposed circuit, the current ripple of the output capacitor depends on the neutral point connections between the modules. In this study, the ripple current is analyzed by the neutral point connections of the three-level boost converter that has a low-level inductor, and the effectiveness of the proposed circuit is proven by simulation and experiment.

• 전력전자학회논문지
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• 제12권3호
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• pp.191-198
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• 2007

소형 BLDC(Brushless DC) 전동기는 높은 운전효율과 고토크 특성으로 인하여, 산업용 기계와 가전기기 및 특히 의료용 장비에 널리 사용되고 있다. 일반적인 BLDC 전동기의 경우에 전류(commutation) 구간에서의 토크 리플 억제에 대한 다양한 연구가 이루어져 왔다. 하지만, 초고속 BLDC 전동기의 경우 설계 특성상 전기적 시정수가 매우 짧아서 전류 구간에서의 토크 리플 보다 통전 구간에서의 토크 리플이 더 큰 영향을 미치게 된다. 본 논문에서는 40000rpm급 초고속 소형 BLDC 전동기의 전기적 시상수에 따른 통전구간에서의 토크리플을 해석하고, 토크 리플 억제를 위하여, 순시 전압 제어기와 고속 히스테리시스 전류 제어기를 제안한다. 제안된 순시 전압제어기는 통전구간에서의 토크 리플 억제를 위하여 운전속도와 부하전류에 적합한 전압을 순시적으로 제어하여 BLDC 전동기에 공급하고, 고속 히스테리시스 전류 제어기는 DSP의 지령전류에 따라, 제어 주기의 샘플링 지연없이 부하전류를 제어하는 시스템이다. 제안된 초고속 소형 BLDC 전동기의 토크 리플 억제를 위한 제어 시스템은 시뮬레이션 및 실험을 통하여 그 타당성을 증명하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 B
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• pp.580-582
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• 2002

A major problems of Switched Reluctance Motor(SRM) is torque ripple which causes undesirable acoustic noise and vibration. To reduce the torque ripple two different approaches are used. One is to modify a motor geometry, the other is to manipulate motor current to improve performance. This paper presents modifications of the rotor pole shape which reduces the torque ripple.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.337-341
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• 1998

Brushless DC motors have trapezoidal back emf waveform. Generally, because it is drived by a voltage source inverter, the ideal rectangular phase current is not available and therefore produce torque ripple. In this paper, the torque ripple due to commutation is analysed and the practical method that can reduce the torque ripple is proposed. Simulation and experimental results show the effectiveness of the proposed method.