• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.142-144
• /
• 2006

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

• Journal of Power Electronics
• /
• v.10 no.1
• /
• pp.21-26
• /
• 2010

The most important feature of the one-cycle control method is its excellent ability in line disturbance rejection. However, when it is used as a controller in dc-dc converters, it has an undesirable transient response. The voltage overshoot at the transient time, which usually exists in one-cycle controlled converters, is unwanted in many applications and it is sometimes hazardous. In this paper, it is shown that the combination of a one-cycle controller with a current mode controller, can improve the transient response and consequently the overshoot can be controlled. Therefore, the combined controller has the excellent line disturbance rejection of a one-cycle controller and the output current limiting capability of current mode controllers. Because in this scheme a one-cycle controller is the master controller, the problem of instability of current mode control, will not happen. By simulation and a practical prototype, the capability of the method is shown.

• Proceedings of the KIPE Conference
• /
• 1998.07a
• /
• pp.275-278
• /
• 1998

The mathematical interpretation of a practical sampler which is useful to obtain the small signal models for the peak and average current mode controls is proposed. Due to the difficulties in applying the Shannon's sampling theorem to the analysis of sampling effects embedded in the current mode control, several different approaches have been reported. However, these approaches require the information of the inductor current in a discrete expression, which restricts the application of the reported method only to the peak current mode control. In this paper, the mathematical expressions of sampling effects on a current loop which can directly apply the Shannon's sampling theorem are newly proposed, and applied to the modeling of the peak current mode control. By the newly derived models of a practical sampler, the models in a discrete time domain and a continuous time domain are obtained. It is expected that the derived models are useful for the control loop design of power supplies. The effectiveness of the derived models are verified through the simulation and experimental results.

• Journal of Power Electronics
• /
• v.19 no.6
• /
• pp.1582-1590
• /
• 2019

A new method for reducing the common-mode current generated by the voltage variations in a two-inverter air conditioner system by applying a synchronized pulse-width modulation (PWM) strategy is proposed. The PWM signals of the master-mode inverter are generated based on the reference voltage, while those of the slave-mode inverter are output in the opposite direction when the master-mode inverter changes its switching state. However, the slave-mode control results in a mismatch between the reference voltage and the actual output voltage that is modified by synchronized control operation. The proposed method is capable of reducing and controlling this voltage error by performing signal selection in the vector space of the slave-mode inverter, which mitigates the distortion of the phase current. The efficacy of this method in reducing conducted emissions has been validated both theoretically and experimentally.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.10 no.12
• /
• pp.3614-3621
• /
• 2009

In this paper, A CMOS low-voltage current mode integrator is designed. The designed current-mode integrator is based on linear cascode circuit that is newly proposed in this paper. When it is compared with gain(43.7dB) and unity gain frequency(15.2MHz) of the typical current-mirror type current-mode integrator, the proposed linear cascode current-mode integrator achieves high current gain(47.8dB) and unity gain frequency(27.8MHz). And a 5th Chebyshev current-mode filter with 7.03MHz cutoff frequency is designed. The designed all circuits are simulated by HSPICE using 1.8V-$0.18{\mu}m$ CMOS technology.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.10 no.12
• /
• pp.3638-3644
• /
• 2009

A CMOS multi-channel low-voltage current mode filter circuit is designed. The designed current-mode filter is based on linear cascode current-mode integrator that is newly proposed in this paper. When it is compared with that of the typical current-mirror type current-mode integrator, the proposed linear cascode current-mode integrator achieves high current gain and unity gain frequency. The designed filter is composed with 5th Chebyshev function and converted to active version by signal flow graph method. We verified that the designed filter can be applied to three-channel basedband, bluetooth, DECT and WCDMA with 0.51MHz~7.03MHz frequency tuning range by Hspice simulation using 1.8V-$0.18{\mu}m$ CMOS technology.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.49 no.2
• /
• pp.116-119
• /
• 2000

A hybrid SOI bipolar-mode field effect transistor (BMFET) is proposed to improve the current gain. The device characteristics are analyzed and verified numerically for BMFET mode, DMOS mode, and hybrid mode by MEDICI simulation. The proposed SOI BMFET exhibits 30 times larger current gain in hybrid-mode operation by connecting DMOS gate to the p+ gate of BMFET structure as compared with the conventional structure without sacrifice of breakdown voltage and leakage current characteristics. This is due to the DMOS-gate-induced hybrid effect that lowers the barrier of p-body and reduces the charge in p-body.

• Journal of Power Electronics
• /
• v.19 no.5
• /
• pp.1142-1152
• /
• 2019

This paper presents a control method for reducing the current distortion in an indirect matrix converter (IMC) operating in boost mode under unbalanced input conditions. IMCs operating in boost mode are useful in distributed generation (DG) systems. They are connected with renewable energy systems (RESs) and the grid to transmit the power generated by the RES. However, under unbalanced voltage conditions of the RES, which is connected with the input stage of the IMC operating in boost mode, the input-output currents are distorted. In particular, the output current distortions cause a ripple of the power, which is transferred to the grid. This aggravates the reliability and stability of the DG system. Therefore, in this paper, a control method using positive/negative sequence voltages and currents is proposed for reducing the current distortion of both side in IMCs operating in boost mode. Simulation and experimental results have been presented to validate effectiveness of the proposed control method.

• ETRI Journal
• /
• v.26 no.4
• /
• pp.292-296
• /
• 2004

In this paper we present a new current-mode electronically tunable universal filter using only plus-type current controlled conveyors (CCCII+s) and grounded capacitors. The proposed circuit can simultaneously realize lowpass, bandpass, and highpass filter functions - all at high impedance outputs. The realization of a notch response does not require additional active elements. The circuit enjoys an independent current control of parameters $\omega_0$ and $\omega_0/Q$. No element matching conditions are imposed. Both its active and passive sensitivities are low.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 2004.05a
• /
• pp.506-510
• /
• 2004

A multi-phase interleaved buck converter is used to reduce current ripples and filter size of a power supply. This paper addresses the modelling and steady-state analysis of the multi-phase interleaved buck converter operated in discontinuous inductor current mode. The model is derived using an averaging technique in steady state. The do voltage ratio and the range of the discontinuous inductor current mode(DICM) and the continuous output current mode(COCM) are derived from the averaged state-space model. In addition, the efficiency is investigated according to the number of phase.