• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.609-614
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• 1998

A new small signal modeling of an average current mode control is proposed. In order to analyze the characteristics of the control scheme, the discrete and continuous time small signal models are derived. The derivation are mainly come from the analysis of the sampling effect presented in the current control loop. By the mathematical interpretation of practical sampler representing the sampling effect of a current control loop, the small signal models of an average current mode control can be easily derived. The instability of the current control loop, which gives rise to the subharmonic oscillation, can be identified by the proposed models. To show the usefulness of the proposed models, the simulation and experiment are carried out. The results show that the predicted results by the proposed model are much better agreed with the measured ones than that of the conventional model, even though the high gain of the compensation network of a current control loop is employed.

• 한국통신학회논문지
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• 제21권7호
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• pp.1726-1733
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• 1996

A 3V-50MHz analog CMOS continuous-time current-mode filter with a negative resistance load(NRL) is proposed. In order to design a current-mode current integrator, a modified basic current mirror with a NRL to increase the output resistance is employed. the inherent circuit structure of the designed NRL current integrator, which minimizes the internal circuit nodes and enhances the gain bandwidth product, is capable of making the filter operate at the high frequency. The third order Butterworth low pass filter utilizing the designed NRL current integrator is synthesized and simulated with a 1.5.mu.m CMOS n-well proess. Simulation result shows the cutoff frequency of 50MHz and power consumption of 2.4mW/pole with a 3V power supply.

• 전력전자학회논문지
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• 제27권5호
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• pp.446-454
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• 2022

This study proposes a carrier-based pulse width modulation (PWM) method for leakage current reduction and neutral point (NP) current control in a three-phase three-level converter, which is a carrier-based PWM version of the previously proposed low-frequency common mode voltage PWM. Three groups of space vectors with the same common mode voltage are used. When the averaged NP current needs to be positive or negative, the specific groups are employed to produce low-frequency common mode voltages. The validity of the proposed PWM method is verified through experiments.

• 전력전자학회논문지
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• 제10권2호
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• pp.162-168
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• 2005

본 논문에서는 전력변환회로를 위한 디지털 전류모드제어기를 소신호 모델식을 기반으로 하여 설계한다. 다양한 응용 가능성을 내포하고 있는 디지털 제어기를 전류모드제어를 사용하는 전력변환회로의 설계에 응용한다. 전력변환회로의 상태평균화 기법을 적용한 연속 시간 소신호 모델을 이용함으로써 부스트, 벅, 벅-부스트 컨버터에 모두 적용 가능한 디지털 전류모드제어기를 설계하고, 설계한 제어기는 모든 시비율 동작 조건에서 안정함을 확인한다. 16bit DSP 마이크로프로세서인 TMS320LF2406A를 사용하여 설계된 디지털 제어기를 구현하고, 아날로그제어기를 이용한 전류모드제어에서의 동작 조건에 따른 불안정성 문제를 해결할 수 있음을 실험을 통해 확인한다.

• 센서학회지
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• 제28권5호
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• pp.284-288
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• 2019

A calibration-free analog neuron circuit is proposed as a viable alternative to the power hungry digital neuron in implementing a deep neural network. The conventional analog neuron requires calibrations because a voltage-mode link is used between the soma and the synapse, which results in significant uncertainty in terms of current mapping. In this work, a current-mode link is used to establish a robust link between the soma and the synapse against the variations in the process and interconnection impedances. The increased hardware owing to the adoption of the current-mode link is estimated to be manageable because the number of neurons in each layer of the neural network is typically bounded. To demonstrate the utility of the proposed analog neuron, a simple neural network with $4{\times}7{\times}3$ architecture has been designed for classifying iris flowers. The chip is now under fabrication in 0.35 mm CMOS technology. Thus, the proposed true current-mode analog neuron can be a practical option in realizing power-efficient neural networks for edge computing.

• 정보처리학회논문지A
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• 제17A권3호
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• pp.121-126
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• 2010

본 논문에서는 저 전압 스윙 기술을 적용하여 저 전력 회로를 구현하고, 슬립 트랜지스터 (sleep-transistor)를 이용하여 누설전류를 최소화하는 새로운 저 전력 MOS 전류모드 논리회로 (MOS current-mode logic circuit)를 제안하였다. 제안한 회로는 저 전압 스윙 기술을 적용하여 저 전력 특성을 갖도록 설계하였고 고 문턱전압 PMOS 트랜지스터 (high-threshold voltage PMOS transistor)를 슬립 트랜지스터로 사용하여 누설전류를 최소화하였다. 제안한 회로는 $16\;{\times}\;16$ 비트 병렬 곱셈기에 적용하여 타당성을 입증하였다. 이 회로는 슬립모드에서 기존 MOS 전류 모드 논리회로 구조에 비해 대기전력소모가 1/104로 감소하였으며, 정상 동작모드에서 11.7 %의 전력소모 감소효과가 있었으며 전력소모와 지연시간의 곱에서 15.1 %의 성능향상이 있었다. 이 회로는 삼성 $0.18\;{\mu}m$ CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.

• 한국음향학회지
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• 제18권2호
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• pp.53-60
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• 1999

본 논문에서는 CSH(Current Sample-and-Hold)와 CCMP(Current Comparator)로 구성된 1.5-비트 비트 셀을 이용한 새로운 구조의 CMOS IADC(Current-mode Analog-to-Digital Convener)를 제안한다. 전체적인 IADC의 선형성 향상을 위하여 CFT(Clock Feedthrough)가 제거된 9-비트 해상도 CSH를 설계하여 각 비트 셀 전단에 배치하였다. 제안한 IADC를 구성하는 비트 셀은 2개의 래치 CCMP를 사용하기 때문에 디지털 교정 로직이 간소화되고 소비전력이 감소된다. 또한 IADC를 구성하는 모든 블록들의 회로는 MOS 트랜지스터로만 설계되었기 때문에 혼성모드 집적화에 유리하다. 제안한 IADC를 현대 0.8 ㎛ CMOS 파라미터로 HSPICE 시뮬레이션 결과, 20Ms/s에서 100 ㎑의 입력 신호에 대한 SNR은 43 dB로 7-비트의 해상도를 만족하였고 27 ㎽의 소비전력 특성을 나타냈다.

• Journal of Power Electronics
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• 제16권5호
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• pp.1813-1820
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• 2016

Dual-mode photovoltaic power system should be capable of operating in grid-connected (GC) and stand-alone (SA) modes for distributed generation. Under different working modes, the optimal parameters of inverter output filters vary. Inverters commonly operate in GC mode, and thus, a small capacitance is beneficial to the GC topology for achieving a reasonable compromise. A predictive current control scheme is proposed to control the grid current in GC mode and thereby obtain high-performance power. As filter are not optimal under SA mode, a compound control strategy consisting of predictive current control, instantaneous voltage control, and repetitive control is proposed to achieve low total harmonic distortion and improve the output voltage spectrum. The seamless transfer between GC mode and SA mode is illustrated in detail. Finally, the simulation and experimental results of a 4 kVA prototype demonstrate the effectiveness of the proposed control strategy.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.399-400
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• 2012

The proposed battery charger presented in this paper is suitable for Lead-Acid Battery and the dc/dc buck converter topology is applied as a charger circuit. The technique adopted in this charger is constant current & constant voltage dual mode, which is decided by the value of voltage of proposed battery. Automatic mode change function is detected by the percentage value of level of battery charging. CC Mode (Constant Current Mode) is operated when charging level is below 80% of the total charging of Battery voltage and above 80% of battery voltage charging, CV Mode (Constant Voltage Mode) is automatically operated. As the charging level exceeds 120%, it automatically terminates charging. The feedback signal to the PWM generator for charging the battery is controlled by using the current and voltage measurement circuits simultaneously. This technique will degrade the damage of proposed type of battery and improve the power efficiency of charger. Finally, a prototype charger circuit designed for a 12-V 7-Ah lead acid battery is constructed and tested to confirm the theoretical predictions. Satisfactory performance is obtained from simulation and the experimental results.

• 전력전자학회논문지
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• 제4권4호
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• pp.325-331
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• 1999

계통연계형 태양광발전시스템에서는 계통과 태양광시스템을 연계하기 위해 PWM 인버터가 이용된다. 인버터 시스템을 연속전류모드로 운전하면 맥동이 발생하게 되고, 직류전류의 맥동발생은 교류전류파형의 왜형을 가져온다. 본 연구에서는 직류입력전류의 맥동을 감소시키기 위하여 불연속모드 승강압초퍼로 인버터를 운전한다. 직류 전류에 포함된 고조파성분을 리플성분과 직류성분으로 분리하여 해석하고, 맥동이 없는 일정한 직류전류를 태양 전지로부터 인버터로 공급한다. 제안하는 인버터시스템은 단위 역률로 부하와 계통에 교류전류를 공급한다.