• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.54-61
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• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.2
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• pp.120-130
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• 1999

In this paper, we show that the instantaneous phase current of the bifiler-wound hybrid stepping motor is dependent of lead angle and that the information of motor position is obtained from the instantaneous phase current at ${\pi}/2$ by the theoretical formular and its computer simulation results. From the facts, we design the microcontroller-based motor position sensorless controller of optimal lead angle, which generates the excitation pulses for the closed-loop drives. The controller is consist of microcontroller which has the function of A/D converter, programmable input/output timer, and the transfer table which has the values of optimal lead angle depending on motor velocity, and ROM which has the transfer table of the values of lead angle depending on velocity of motor and the values of instantaneous phase current at ${\pi}/2$. From the design of microcontroller-based controller, we minimize the external interface circuit and obtain flexibility by changing the contents of ROM transfer tables and the control software. We confirm that the designed controller drives the bifilar-wound hybrid stepping motor is the mode of optimal lead angle by comparing the instananeous phase current experimental results and computer simulation results.

• Journal of the Korean Vacuum Society
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• v.19 no.1
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• pp.52-57
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• 2010

$BiFeO_3/Pb(Zr_{0.52}Ti_{0.48})O_3$(BFO/PZT) multilayer thin films have been prepared on a Pt/Ti/$SiO_2$/Si(100) substrate by chemical solution deposition. BFO single layer, BFO/PZT bilayer and multilayer thin films were studied for comparison. X-ray diffraction analysis showed that the crystal structure of all films was multi-orientated perovskite phase without amorphous and impurity phase. The leakage current density at 500 kV/cm was reduced by approximately four and five orders of magnitude by bilayer and multilayer structure films, compared with BFO single layer film. The low leakage current density leads to saturated P-E hysteresis loops of bilayer and multilayer films. In BFO/PZT multlayer film, saturated remanent polarization of $44.3{\mu}C/cm^2$ was obtained at room temperature at 1 kHz with the coercive field($2E_c$) of 681.4 kV/cm.

• Proceedings of the KOR-KST Conference
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• 1995.12a
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• pp.45-73
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• 1995

The current paper presents a system dynamics model which can generate the land use anq transportation system performance simultaneously is proposed. The model system consists of 7 submodels (population, migration of population, household, job growth-employment-land availability, housing development, travel demand, and traffic congestion level), and each of them is designed based on the causality functions and feedback loop structure between a large number of physical, socio-economic, and policy variables. The important advantages of the system dynamics model are as follows. First, the model can address the complex interactions between land use and transportation system performance dynamically. Therefore, it can be an effective tool for evaluating the time-by-time effect of a policy over time horizons. Secondly, the system dynamics model is not relied on the assumption of equilibrium state of urban systems as in conventional models since it determines the state of model components directly through dynamic system simulation. Thirdly, the system dynamics model is very flexible in reflecting new features, such as a policy, a new phenomenon which has not existed in the past, a special event, or a useful concept from other methodology, since it consists of a lots of separated equations. In Chapter I, II, and III, overall approach and structure of the model system are discussed with causal-loop diagrams and major equations. In Chapter V _, the performance of the developed model is applied to the analysis of the impact of highway capacity expansion on land use for the area of Montgomery County, MD. The year-by-year impacts of highway capacity expansion on congestion level and land use are analyzed with some possible scenarios for the highway capacity expansion. This is a first comprehensive attempt to use dynamic system simulation modeling in simultaneous treatment of land use and transportation system interactions. The model structure is not very elaborate mainly due to the problem of the availability of behavioral data, but the model performance results indicate that the proposed approach can be a promising one in dealing comprehensively with complicated urban land use/transportation system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8A
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• pp.918-927
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• 2004

WCDMA system is 3rd generation wireless mobile system specified by 3GPP. In WCDMA downlink, two power control schemes are operated. One is inner loop power control operated in every slot. Another is outer loop power control based on one frame time. Base station (BS) can estimate proper transmission power by these two power control schemes. However, because each MS's transmission power makes a severe effect on BS's performance, BS cannot give excessive transmission power to the specific user. 3GPP defined Power Control Dynamic Range (PCDR) to guarantee proper BS's performance. In this paper, we propose Adaptive PCDR algorithm. By APCDR algorithm, Radio Network Controller (RNC) can estimate each MS's current state using received signal to interference ratio (SIR). APCDR algorithm changes MS's maximum code channel power based on frame. By proposed scheme, each MS can reduce wireless channel effect and endure outages in cell edge. Therefore, each MS can obtain better QoS. Simulation result indicate that APCDR algorithm show more attractive output than fixed PCDR algorithm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.35-40
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• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.

• Journal of Sensor Science and Technology
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• v.5 no.2
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• pp.29-36
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• 1996

With the three dimensional magnetic field measuring system dealt with in this paper, accurate measurements and analyses of extremely low frequency(ELF) magnetic fields caused by starting and/or operating electric devices and power installations can be conducted. To obtain high performance for lower frequency and spatial components without any distortion, the measuring system is designed as three dimensionally including the multiturn loop-type magnetic field sensors, differential amplifiers and active integrators. As the results of calibration experiments, the frequency response characteristics of the measuring system range from 8[Hz] to about 53[kHz] for each direction of x, y, z axes, and the response sensitivities are 9.54, 9.21, $10.89[mV/{\mu}T]$, respectively. The actual survey experiments by using an oscillating impulse current generator confirm a reliability of the proposed measuring system. Also, through the other experiments by using small-sized induction motors, the magnetic field intensities when starting and steady-state operating mark 15.8, $8.61[{\mu}T]$ as maximum value, respectively. And those intensities decrease steeply according as the measuring distance increases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.126-142
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• 2016

This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.1048-1057
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• 2004

WCDMA system is 3rd generation wireless mobile system specified by 3GPP. In WCDMA downlink, two power control schemes are operated. One is inner loop power control operated m every slot Another is outer loop power control based on one frame time. Base staion (BS) can estimate proper transmission power by these two power control schemes. However, because each MS's transmission power makes a severe effect on BS's performance, BS cannot give excessive transmission power to the speclfic user 3GPP defined Power Control Dynamic Range (PCDR) to guarantee proper BS's performance. In this paper, we propose Adaptive PCDR algorithm. By APCDR algorithm, Radio Network Controller (RNC) can estimate each MS's current state using received signal to interference ratio (SIR) APCDR algorithm changes MS's maximum code channel power based on frame. By proposed scheme, each MS can reduce wireless channel effect and endure outages in cell edge. Therefore, each MS can obtain better QoS. Simulation result indicate that APCDR algorithm show more attractive output than fixed PCDR algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.69-76
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• 2008

This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.