• Title/Summary/Keyword: current comparator

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A Study on Automatic Multi-Power Synchronous Transfer Switch using New DFT Comparator (새로운 DFT 비교기를 이용한 자동 다전원 동기절체 스위치에 관한 연구)

  • Kwak, A-Rim;Park, Seong-Mi;Son, Gyung-Jong;Park, Sung-Jun;Kim, Jong-Cheol
    • Journal of the Korean Society of Industry Convergence
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    • v.25 no.3
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    • pp.423-431
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    • 2022
  • The UPS(Uninterruptible Power Supply) system operates in the battery charging mode when the grid is normal, and in the UPS mode, which is the battery discharge mode when a grid error occurs. Since the UPS must supply the same voltage as the grid to the load within 4 [ms] in case of a grid error, the switching time and power recovery time should be short when controlling the output voltage and current of the UPS, and the power failure detection time is also important. The power outage detection algorithm using DFT(Discrete Fourier Transform) proposed in this paper compares the grid voltage waveform with the voltage waveform including the 9th harmonic generated through DFT using Schmitt trigger to detect power outage faster than the existing power outage monitoring algorithm. There are advantages. Therefore, it is possible to supply instant and stable power when switching modes in the UPS system. The multi-power-applied UPS system proposed in this paper uses DFT, which is faster than the conventional blackout monitoring algorithm in detecting power failure, to provide stable power to the load in a shorter time than the existing power outage monitoring algorithm when a system error occurs. The detection method was applied. The changeover time of mode switching was set to less than 4 [ms], which is 1/4 of the system cycle, in accordance with KSC 4310 regulation, which was established by the Industrial Standards Council on the regulation of uninterruptible power supply. A 10 [kW] UPS system in which commercial voltage, vehicle generator, and auxiliary diesel generator can be connected to each of the proposed transfer devices was constructed and the feasibility was verified by conducting an experiment.

A Design of Transceiver for 13.56MHz RFID Reader using the Peak Detector with Automatic Reference Voltage Generator (자동 기준전압 생성 피크 검출기를 이용한 13.56 MHz RFID 리더기용 송수신기 설계)

  • Kim, Ju-Seong;Min, Kyung-Jik;Nam, Chul;Hurh, Djyoung;Lee, Kang-Yun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.3
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    • pp.28-34
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    • 2010
  • In this paper, the transceiver for RFID reader using 13.56MHz as a carrier frequency and meeting International Standard ISO 14443 type A, 14443 type B and 15693 is presented. The receiver is composed of envelope detector, VGA(Variable Gain Amplifier), filter, comparator to recovery the received signal. The proposed automatic reference voltage generator, positive peak detector, negative peak detector, and data slicer circuit can adjust the decision level of reference voltage over the received signal amplitudes. The transmitter is designed to drive high voltage and current to meet the 15693 specification. By using inductor loading circuit which can swing more than power supply and drive large current even under low impedance condition, it can control modulation rate from 30 percent to 5 percent, 100 perccnt and drive the output currents from 5 mA to 240 mA depending on standards. The 13.56 MHZ RFID reader is implemented in $0.18\;{\mu}m$ CM08 technology at 3.3V single supply. The chip area excluding pads is $1.5mm\;{\times}\;1.5mm$.

A 0.2V DC/DC Boost Converter with Regulated Output for Thermoelectric Energy Harvesting (열전 에너지 하베스팅을 위한 안정화된 출력을 갖는 0.2V DC/DC 부스트 변환기)

  • Cho, Yong-hwan;Kang, Bo-kyung;Kim, Sun-hui;Yang, Min-Jae;Yoon, Eun-jung;Yu, Chong-gun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.10a
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    • pp.565-568
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    • 2014
  • This paper presents a 0.2V DC/DC boost converter with regulated output for thermoelectric energy harvesting. To use low voltages from a thermoelectric device, a start-up circuit consisting of native NMOS transistors and resistors boosts an internal VDD, and the boosted VDD is used to operate the internal control block. When the VDD reaches a predefined value, a detector circuit makes the start-up block turn off to minimize current consumption. The final boosted VSTO is achieved by alternately operating the sub-boost converter for VDD and the main boost converter for VSTO according to the comparator outputs. When the VSTO reaches 2.4V, a buck converter starts to operate to generate a stabilized output VOUT. Simulation results shows that the designed converter generates a regulated 1.8V output from an input voltage of 0.2V, and its maximum power efficiency is 60%. The chip designed using a $0.35{\mu}m$ CMOS process occupies $1.1mm{\times}1.0mm$ including pads.

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A 0.31pJ/conv-step 13b 100MS/s 0.13um CMOS ADC for 3G Communication Systems (3G 통신 시스템 응용을 위한 0.31pJ/conv-step의 13비트 100MS/s 0.13um CMOS A/D 변환기)

  • Lee, Dong-Suk;Lee, Myung-Hwan;Kwon, Yi-Gi;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.3
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    • pp.75-85
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    • 2009
  • This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.