• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.87-94
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• 2001

A soft error rate for DRAM was predicted in connection with the leakage current in cell capacitor. The charge in cell capacitor was decreased during the DRAM operation, and soft error retes due to the leakage current were calculated in various operation mode of DRAM. It was found that the soft error rate of the /bit mode was dominant with small leakage current, but as increasing the leakage current memory mode shown the dominant effect on soft error rate. Using the 256M grade DRAM structure it was predicted that the soft error rate was influenced by the change of the cell capacitance, bit line capacitance, and the input voltage sensitivity of sense amplifier, and these results can be used to the design of the optimum cells in the next generation DRAM development.

• ETRI Journal
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• v.31 no.5
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• pp.598-600
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• 2009

A highly efficient and compactly integrated balanced power amplifier (PA) for W-CDMA handset applications is presented. To overcome the size limit of a typical balanced PA, a bulky input divider is integrated into a PA MMIC, and a complex output network is replaced with simple lumped-element networks. For efficiency improvement at the low output power level, one of the two amplifiers in parallel is deactivated and the other is partially operated with corresponding load impedance optimization. The implemented PA shows excellent average current consumption of 34.5 mA in urban and 56.3 mA in suburban environments, while exhibiting very good load-insensitivity under condition of VSWR=4:1.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.91-95
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• 2008

This paper presents a direct-conversion I/Q up-mixer block, which supports $3{\sim}5$ GHz ultra-wideband(UWB) applications. It consists of a VI converter, a double-balanced mixer, a RF amplifier, and a differential-to-single signal converter. To achieve wideband characteristics over $3{\sim}5$ GHz frequency range, the double-balanced mixer adopts a shunt-peaking load. The proposed RF amplifier can suppress unwanted common-mode input signals with high linearity. The proposed direct-conversion I/Q up-mixer block is implemented using $0.18-{\mu}m$ CMOS technology. The measured results for three channels show a power gain of $-2{\sim}-9$ dB with a gain flatness of 1dB, a maximum output power level of $-7{\sim}-14.5$ dBm, and a output return loss of more than - 8.8 dB. The current consumption of the fabricated chip is 25.2 mA from a 1.8 V power supply.

• Journal of electromagnetic engineering and science
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• v.2 no.1
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• pp.5-10
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• 2002

We have analized the inverse class-F and class-F amplifiers using their waveforms. From the analytic equations derived from the analysis, we have calculated tole efficiencies, output powers, DC power dissipations, and optimum fundamental load impedances of the inverse class-F and class-F amplifiers. We also have compared them for various operation conditions, which include the same peak current, saute DC power dissipation, same fundamental RF output power, and same fundamental load impedance with different Ron(on-resistance). These analyses have clearly shown the performance limitations, advantages, and guide to the optimized design of the inverse class-F amplifiers.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.364-366
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• 2009

광 바이오 센서 시스템에서 Trans-Impedance amplifier (TIA)는 광검출기로부터 입력단으로 들어오는 미세한 전기 신호를 원하는 신호레벨까지 증폭하는 역할을 한다. TIA는 광 바이오 센서 시스템의 감도 (sensitivity)를 결정하는 매우 중요한 회로로 저잡음, 저전력, 낮은 입력 임피던스 등의 특성이 요구되어진다. 본 논문에서는 광 바이오 센서 시스템에서 요구되어 지는 저전력, 저잡음 성능을 구현하기 위하여 regulated cascode (RGC) TIA를 설계하였다. 본 연구에서는 기존 common gate (CG) 기법의 TIA에서 전류원 역할을 하는 current source를 저항으로 대체하고, local feedback stage를 이용하는 RGC TIA를 저잡음, 저전력 특성 및 회로 면적 감소의 장점을 갖도록 설계하였다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.521-522
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• 2008

This paper presents fully integrated low power consumption limiting amplifier. The proposed limiting amplifier is employed folded cascode structure with source degeneration output stage. This proposed structure demands few transconductance than conventional structure. It can be dramatically decrease current consumption. The total power consumption is only $96.5\;{\mu}W$ under a 1.8 V supply voltage in 9.5 dB limited gain condition. It was designed in using $0.18\;{\mu}m$ CMOS technology.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.104-107
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• 2000

We designed and implemented the RFIC(RF front-end IC) for DTV(Digital TV) tuner. The DTV tuner RF front-end consists of low noise IF amplifier fur the amplification of 900 MHz RF signal and down conversion mixer for the RF signal to 44MHz IF conversion. The RFIC is implemented on ETRI 0.8u high resistive (2㎘ -cm) and evaluated by on wafer, packaged chip test. The gain and IIP3 of IF amplifier are 15㏈ and -6.6㏈m respectively. For the down conversion mixer gain and IIP3 are 13㏈ and -6.5㏈m. Operating voltage of the IF amplifier and the down mixer is 5V, current consumption are 13㎃ and 26㎃ respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.283-288
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• 2008

A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation ($IM_3$) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using $0.18-{\mu}m$ technology. The LNA achieved +10.2 dBm IIP3 with 13.7 dB gain and 1.68 dB NF at 2 GHz consuming 11.8 mA from a 1.8-V supply. It shows IIP3 improvement by 6.6 dB over the conventional cascode LNA without the linearizing circuit.

• Journal of Sensor Science and Technology
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• v.18 no.4
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• pp.280-285
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• 2009

In this paper, we designed a 2-stage CMOS operational amplifier with temperature compensation function using 2-poly 4-metal 0.35 $\mu$m standard CMOS technology. Using two bias circuits, the positive temperature coefficient(PTC) and the negative temperature coefficient(NTC) of the bias circuit are canceled out each other. When reference current circuit is simulated that it has a temperature coefficient of -150 ppm/$^{\circ}C$ with a temperature change from 0 $^{\circ}C$ to 120 $^{\circ}C$. Also the proposed circuit has a temperature coefficient of -0.011 dB/$^{\circ}C$ of DC open loop gain with the same temperature range.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1121-1133
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• 1998

In this paper, a new method is proposed for a simple andaccurate design of larage-sigal power amplifier using the output current- and volage- waveform analysis. An existing high-efficiency theory, Harmonic Loading, is modified to apply to a real device, and the notion of "actual bias point at large-signal input" is proposed. Based on the proposed theory, 2GHz band poweramplifier is implemented using HEMT device, and the implemented amplifier shows 14dBm output power, 46% drain efficienty, 38% power-added efficiency and 7.8dB gain at 2V bias voltage.