• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of Advanced Navigation Technology
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• v.28 no.3
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• pp.348-355
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• 2024

A current source capable of stably supplying current as a measurement medium is required in order to measure and test important facilities that require large-scale measurement current, such as a control element drive mechanism control system(CEDMCS), in case of dismantling a nuclear power plant. However, it can provides only voltage power as a source, not current, although direct voltage controlled constant current source is essential to test major equipment. That kind of source is not available to supply stable constant current regardless of load variation. It is just voltage supplier. Developing current source is not easy other than voltage source. Very large-scale current source up to ampere class more than such ten times of normal current is inevitable to test above mentioned equipment. So, we developed large-scale current source which is controlled by input DC voltage and supplies constant stable current to object equipment according to this requirement. We measured and tested nuclear power plant equipment using given real site data for a long time and afforded long period load test, and then proved its validity and verification. The developed invetion will be used future installed important equipment measuring and testing.

• Geophysics and Geophysical Exploration
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• v.8 no.3
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• pp.224-231
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• 2005

In geophysical field surveys, commercial equipments often fail to resolve the subsurface target or even sometimes fail to be applied because they do not fit to the various field situations or the physical properties of the medium or target. We developed a geophysical measurement system, which can be easily adapted for the various field situations and targets. The system based on PXI with A/D converter and some stand alone equipment such as Network Analyzer was applied to borehole radar survey, borehole sonic measurement and electromagnetic noise measurement. The system for borehole radar survey consists of PXI, Network Analyzer, dipole antennas, GPIB interface is used for PXI to control Network Analyzer. The system for borehole sonic measurement consists of PXI, 24 Bit A/D converter, high voltage pulse generator, transmitting and receiving piezoelectric sensors. The electromagnetic noise measurement system consists of PXI, 24 Bit A/D converter, 2 horizontal component electric field sensors and 2 horizontal and 1 vertical component magnetic filed sensors. The borehole radar system has been successfully applied to detect the width of the artificial tunnel through which the borehole pass and to image buried steel pipe, while the commercial borehole radar equipment failed. The borehole sonic system was tested to detect the width of artificial tunnel and showed a reasonable result. The characteristic of electromagnetic noise was grasped at an urban area with the data from the electromagnetic noise measurement system. The system is also applied to characterize the signal distortion by induction between the electric cables in resistivity survey. The system can be applied various geophysical problems with a simple modification of the system and sensors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1154-1162
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• 2016

This paper proposes a fast-transient digital LDO(Low dropout) regulator with binary-weighted current control technique. Conventional digital LDO takes a long time to stabilize the output voltage, because it controls the amount of current step by step, thus ringing problem is generated. Binary-weighted current control technique rapidly stabilizes output voltage by removing the ringing problem. When output voltage reliably reaches the target voltage, It added the FRZ mode(Freeze) to stop the operation of digital LDO. The proposed fast response digital LDO is used with a slow response DC-DC converter in the system which rapidly changes output voltage. The proposed digital controller circuit area was reduced by 56% compared to conventional bidirectional shift register, and the ripple voltage was reduced by 87%. A chip was implemented with a $0.18{\mu}F$ CMOS process. The settling time is $3.1{\mu}F$ and the voltage ripple is 6.2mV when $1{\mu}F$ output capacitor is used.

• Journal of the Korea Society of Computer and Information
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• v.10 no.5 s.37
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• pp.123-132
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• 2005

In this Paper, we present an improvement of switch node for wavelength multiplex optical network. Currently because of quick increase of internet traffic a big network capacity is demanded. Wavelength multiplex optical network Provides the data transfer of high speed and the transparent characteristic of the data. Therefore optic network configuration is the most powerful technology in the future. It will be able to control the massive traffic from the optical network in order to transmit the multimedia information of very many quantify. Consequently the node where the traffic control is Possible, is demanded. The optical switch node which manages efficiently the multiple wavelength was Proposed. This switch is composed of a optical switch module for switching and a wavelength converter module for wavelength conversion. It will be able to compose the switch fabric without optical/electro or electro/optical conversion using optical MEMS(Micro Electro Mechanical Switches) module. Finally, we present the good test result regarding the operational qualify of the switch fabric and the performance of optical signal from the switch node. The proposed switch node of the optic network will be able to control the massive traffic with all optical.

• Journal of Ocean Engineering and Technology
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• v.33 no.2
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• pp.168-177
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• 2019

KRISO (Korea Research Institute of Ship & Ocean Engineering) started a project to develop the core algorithms for autonomous intervention using an underwater robot in 2017. This paper introduces the development of the robot platform for the core algorithms, which is an ROV (Remotely Operated Vehicle) type with one 7-function manipulator. Before the detailed design of the robot platform, the 7E-MINI arm of the ECA Group was selected as the manipulator. It is an electrical type, with a weight of 51 kg in air (30 kg in water) and a full reach of 1.4 m. To design a platform with a small size and light weight to fit in a water tank, the medium-size manipulator was placed on the center of platform, and the structural analysis of the body frame was conducted by ABAQUS. The robot had an IMU (Inertial Measurement Unit), a DVL (Doppler Velocity Log), and a depth sensor for measuring the underwater position and attitude. To control the robot motion, eight thrusters were installed, four for vertical and the rest for horizontal motion. The operation system was composed of an on-board control station and operation S/W. The former included devices such as a 300 VDC power supplier, Fiber-Optic (F/O) to Ethernet communication converter, and main control PC. The latter was developed using an ROS (Robot Operation System) based on Linux. The basic performance of the manufactured robot platform was verified through a water tank test, where the robot was manually operated using a joystick, and the robot motion and attitude variation that resulted from the manipulator movement were closely observed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.400-402
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• 2019

The electric point machine, which is used for the control of the turnout used to change the track of the train, is very important in the railway system. Various wired and wireless real-time monitoring systems are used to check the status of the point machine, but there is a possibility of malfunction due to sensor or network error. In this paper, a redundant monitoring system was designed that incorporates the point machine monitoring system and the CCTV camera control system to double check the operation of the point machine. In the point machine monitoring system, the operating state of the railway converter is monitored, alarmed and transmitted over the network. The CCTV camera control system, which received this information, was required to record the status of the turnout and the point machine in question and send it to the administrator. The manager of the railway line can check the conversion status of the railway through the monitoring screen for the railway line switcher first, and then confirm the switching status directly through the CCTV camera image, thereby improving the reliability of the point machine operation. It will also enable the safe and efficient operation of personnel for management. It is expected to contribute to preventing a derailment caused by a malfunction of the point machine.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.1
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• pp.466-474
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• 2014

This paper presents the line contention avoidance experiments with an optical switch, which was selected based on the comparison analysis and evaluation of the various characteristics. For example, the function, structure, strengths and weaknesses of the optical switches. After considering the nonblocking, modularity, upgrade ability and optical power loss of the several kind of the switch fabrics, a switch was selected. The selected switch fabric by using wavelength converters was controlled to avoid contention of the optical lines. In this experiment shows an example of three cases. As a result of this experiment, optical signal shows a changed peek of optical power in output. By showing a peak it confirms that the contention was avoided. By analyzing of changed optical power according to the channel setting time and release time to control of the switch could be determined. If this analysis applied to the network design, economical and efficient structures can be formed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.