• Title/Summary/Keyword: constant output

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Doherty Amplifier Design Using a Compact Slow-Wave Microstrip Branch-Line coupler for Linearity Improvement (Compact Slow-Wave Microstrip Branch-Line Coupler를 이용한 도허티 증폭기의 선형성 개선)

  • Kim, Tae-Hyung;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.9
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    • pp.55-59
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    • 2008
  • In this paper, the linearity of Doherty amplifier has been improved by applying a compact slow-wave microstrip branch-line coupler on the output of Doherty amplifier. The proposed branch coupler has four microstrip high-low impedance resonant cells periodically placed inside the branch-line coupler to result in high slow-wave effect. The new coupler not only effectively reduces the occupied area to 30% of the conventional branch-line coupler at 1.8GHz, but also has high second harmonic suppression performance. We obtained the 3rd-order intermodulation distortion ($IMD_3$) of -31.16 dBc for CDMA applications with that of maintaining the constant power added efficiency (PAE). The IMD3 performance is improved as much as -7 dBc compared with a Doherty amplifier.

Design of a CMOS IF PLL Frequency Synthesizer (CMOS IF PLL 주파수합성기 설계)

  • 김유환;권덕기;문요섭;박종태;유종근
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.8
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    • pp.598-609
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    • 2003
  • This paper describes a CMOS IF PLL frequency synthesizer. The designed frequency synthesizer can be programmed to operate at various intermediate frequencies using different external LC-tanks. The VCO with automatic amplitude control provides constant output power independent of the Q-factor of the external LC-tank. The designed frequency divider includes an 8/9 or 16/17 dual-modulus prescaler and can be programmed to operate at different frequencies by external serial data for various applications. The designed circuit is fabricated using a 0.35${\mu}{\textrm}{m}$ n-well CMOS process. Measurement results show that the phase noise is 114dBc/Hz@100kHz and the lock time is less than 300$mutextrm{s}$. It consumes 16mW from 3V supply. The die area is 730${\mu}{\textrm}{m}$$\times$950${\mu}{\textrm}{m}$.

A new finite element procedure for fatigue life prediction of AL6061 plates under multiaxial loadings

  • Tarar, Wasim;Herman Shen, M.H.;George, Tommy;Cross, Charles
    • Structural Engineering and Mechanics
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    • v.35 no.5
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    • pp.571-592
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    • 2010
  • An energy-based fatigue life prediction framework was previously developed by the authors for prediction of axial, bending and shear fatigue life at various stress ratios. The framework for the prediction of fatigue life via energy analysis was based on a new constitutive law, which states the following: the amount of energy required to fracture a material is constant. In the first part of this study, energy expressions that construct the constitutive law are equated in the form of total strain energy and the distortion energy dissipated in a fatigue cycle. The resulting equation is further evaluated to acquire the equivalent stress per cycle using energy based methodologies. The equivalent stress expressions are developed both for biaxial and multiaxial fatigue loads and are used to predict the number of cycles to failure based on previously developed prediction criterion. The equivalent stress expressions developed in this study are further used in a new finite element procedure to predict the fatigue life for two and three dimensional structures. In the second part of this study, a new Quadrilateral fatigue finite element is developed through integration of constitutive law into minimum potential energy formulation. This new QUAD-4 element is capable of simulating biaxial fatigue problems. The final output of this finite element analysis both using equivalent stress approach and using the new QUAD-4 fatigue element, is in the form of number of cycles to failure for each element on a scale in ascending or descending order. Therefore, the new finite element framework can provide the number of cycles to failure at each location in gas turbine engine structural components. In order to obtain experimental data for comparison, an Al6061-T6 plate is tested using a previously developed vibration based testing framework. The finite element analysis is performed for Al6061-T6 aluminum and the results are compared with experimental results.

Pulse 2 kW RF Limiter at S-band (S-대역 펄스 2 kW RF 리미터)

  • Jeong, Myung-Deuk
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.7
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    • pp.791-796
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    • 2012
  • A RF limiter is a component to protect the receiver front end from undesired signal. A RF limiter is a key component whose output is constant level for all inputs above a critical value. A RF limiter use a diode to pass signals of low power while attenuating those above some threshold. A RF limiter for receiver protection in modern radar systems is playing a vital role in order to meet challenges of new interference threats and complicated electromagnetic environments. This paper proposed a new circuit for high power RF limiter whose structure is the combination of the PIN diode and Limit diode. PIN diode take a use of its isolation characteristics which act as a switch does. A 2 kW RF limiter with 200 us pulse width at S-band was developed. It shows good agreements between estimated value and measured results.

Design of a 6~18 GHz 8-Bit True Time Delay Using 0.18-㎛ CMOS (0.18-㎛ CMOS 공정을 이용한 6~18 GHz 8-비트 실시간 지연 회로 설계)

  • Lee, Sanghoon;Na, Yunsik;Lee, Sungho;Lee, Sung Chul;Seo, Munkyo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.11
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    • pp.924-927
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    • 2017
  • This paper presents a 6~18 GHz 8-bit true time delay (TTD) circuit. The unit delay circuit is based on m-derived filter with relatively constant group delay. The designed 8-bit TTD is implemented with two single-pole double-throw (SPDT) switches and seven double- pole double-throw (DPDT) switches. The reflection characteristics are improved by using inductors. The designed 8-bit TTD was fabricated using $0.18{\mu}m$ CMOS. The measured delay control range was 250 ps with 1 ps of delay resolution. The measured RMS group delay error was less than 11 ps at 6~18 GHz. The measured input/output return losses are better than 10 dB. The chip consumes zero power at 1.8 V supply. The chip size is $2.36{\times}1.04mm^2$.

Discharging Voltage Control with Error Detecting for Search light of Ship (선박용 탐사조명 전원장치의 방전개시전압 제어와 조명 이상검출)

  • Park, Noh-Sik;Kwon, Soon-Jae;Lee, Dong-Hee
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.22 no.10
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    • pp.8-17
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    • 2008
  • This paper presents a stable lighting method for HID lamp for ship from initial discharging current limit with discharging voltage control. The output voltage of the proposed control scheme is boosted for ignition, and the charging voltage is decreased by the resistor discharging. The proposed controller fires the initial discharge at the designed discharging voltage to limit the discharge current. After the discharging, constant current controller is used for brightness in steady state. The proposed control scheme can limit the initial discharge current using the starting point control without a complex voltage controller. so it can improve the life-time of HID lamp and get a stable discharge from restricted the initial discharge current. In order to improve the protection of the system, a simple instantaneous error detecting circuit for open state and short state of HID lamp is used. The proposed error detecting of HID lamp can protect the power system of lamp control. The effectiveness of the proposed controller is verified from the experiments of practical 2.5[kW] HID search light for ship.

Design and Fabrication of a Active Resonator Oscillator using Active Inductor and Active Capacitor with Negative Resistance (부성저항 특성을 갖는 능동 인덕터와 능동 캐패시터를 이용한 능동 공진 발진기 설계 및 제작)

  • 신용환;임영석
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.8
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    • pp.1591-1597
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    • 2003
  • In this paper, Active Resonator Oscillator using active inductor and active capacitor with HEMTs(agilent ATF­34143) is designed and fabricated. Active inductor with ­25$\Omega$ and 2.4nH in 5.5GHz frequency band and Active capacitor with ­14$\Omega$ and 0.35pF is designed. Active Resonator Oscillator for LO in ISM band(5.8GHz) is designed with active inductor and active capacitor. Active Resonator Oscillator has been simulated by Agilent ADS 2002C. Active Resonator oscillator implemented on the substrate which has the relative dielectric constant of 3.38, the height of 0.508mm, and metal thickness of 0.018mm. This Active Resonator Oscillator shows the oscillation frequency of 5.68GHz with the output power of ­3.6㏈m and phase noise of ­81㏈c/Hz at the offset frequency of 100KHz.

Design of the Call Admission Control System of the ATM Networks Using the Fuzzy Neural Networks (퍼지 신경망을 이용한 ATM망의 호 수락 제어 시스템의 설계)

  • Yoo, Jae-Taek;Kim, Choon-Seop;Kim, Yong-Woo;Kim, Young-Han;Lee, Kwang-Hyung
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.8
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    • pp.2070-2079
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    • 1997
  • In this paper, we proposed the FNCAC (fuzzy neural call admission control) scheme of the ATM networks which used the benefits of fuzzy logic controller and the learning abilities of the neural network to solve the call admission control problems. The new call in ATM networks is connected if QoS(quality of service) of the current calls is not affected due to the connection of a new call. The neural network CAC(call admission control) system is predictable system because the neural network is able to learn by the input/output pattern. We applied the fuzzy inference on the learning rate and momentum constant for improving the learning speed of the fuzzy neural network. The excellence of the proposed algorithm was verified using measurement of learning numbers in the traditional neural network method and fuzzy neural network method by simulation. We found that the learning speed of the FNCAC based on the fuzzy learning rules is 5 times faster than that of the CAC method based on the traditional neural network theory.

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Multi-Band RF Energy Harvesting System Using Buck-Boost DC-DC Converter (Buck-Boost DC-DC Converter를 이용한 다중 대역 RF 에너지 수집 시스템)

  • Cho, Choon Sik
    • Journal of Satellite, Information and Communications
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    • v.12 no.2
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    • pp.89-93
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    • 2017
  • This paper introduces an energy harvesting system that generates energy by collecting multi-band RF signals using buck-boost DC-DC converter. In an environment where the resistance of load using the collected electric energy is constantly changing, a buck-boost DC-DC converter is used in which the input resistance of the DC-DC converter does not change even if the load resistance changes. Since the frequency band of the input RF signal varies, the rectifier is designed for each band so that multiple bands can be processed, and a matching circuit is added to each band in front of the rectifier. For a rectifier to collect very small RF signals, a circuit is designed so that a constant voltage is obtained according to a very small input signal by devising a method of continuously accumulating the voltages collected and generated in each band. It is confirmed that the output efficiency can reach up to 20% even for the RF signal having the input of -20 dBm.

Resistive Current Mode Control for the Solar Array Regulator of SPACE Power System (인공위성 시스템을 위한 태양전지 전력조절기의 저항제어)

  • Bae, Hyun-Su;Yang, Jeong-Hwan;Lee, Jae-Ho;Cho, Bo-Hyung
    • The Transactions of the Korean Institute of Power Electronics
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    • v.11 no.6
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    • pp.535-542
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    • 2006
  • A large signal stability analysis of the solar array regulator system is performed to facilitate the design and analysis of a Low-Earth-Orbit satellite power system. The effective load characteristics of every controllable method in the solar array system are classified to analyze the large signal stability. Then, using the state plane analysis technique, the stability of various equilibrium points is analyzed. A nonlinear transformation algorithm, which changes the effective load characteristic of the solar array regulator as constant resistive load, is also proposed for the large signal stability. The proposed resistive current mode control system can control the solar array output for purposes such as peak power tracking control and battery charging control. For the verification of the proposed large signal analysis and resistive current mode control, a solar array regulator system consisting of two 100W parallel module buck converters has been built and tested using a real 200W solar array.