• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2006년도 추계 학술대회논문집
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• pp.207-207
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• 2006

Hardware technologies for high-performance computing has been developing continuously. However, actual performance of software cannot keep up with the speed of development in hardware technologies, because hardware architectures become more and more complicated and hardware scales become larger. So, software technique to utilize high-performance computing systems more efficiently plays more important role in realizing high-performance computing for computational science. In this paper, the effort to enhance software performance on large and complex high-performance computing systems such as performance optimization and parallelization will be presented. Our effort to serve high-performance computational kernels such as high-performance sparse solvers and the achievements through this effort also will be introduced.

• ETRI Journal
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• 제39권5호
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• pp.632-642
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• 2017

Digital all-optical parallel computing is an important research direction and spans conventional devices and convergent nano-optics deployments. Optical bus-based interconnects provide interesting aspects such as relative information communication speed-up or slow-down between optical signals. This aspect is harnessed in the newly proposed All-Optical Linear Array with a Reconfigurable Pipelined Bus System (OLARPBS) model. However, the physical realization of such communication interconnects needs to be considered. This paper considers spatial layouts of processing elements along with the optical bus light paths that are necessary to realize the corresponding interconnection requirements. A metric in terms of the degree of required physical constraint is developed to characterize the variety of possible solutions. Simple algorithms that determine spatial layouts are given. It is shown that certain communication interconnection structures have associated intrinsic topologies.

• 한국건축시공학회:학술대회논문집
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• 한국건축시공학회 2011년도 춘계 학술논문 발표대회 1부
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• pp.145-148
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• 2011

As a futuristic construction model, building information model(BIM) based project management system(PMIS) and mobile PMIS have been showing visible sign. However, researches on the 3D BIM based PMIS using mobile device are hard to find, result from limitation of mobile device application(slow speed at huge BIM file, display size, and etc.) and undefined standard of business processes. Therefore, this research aims at studying feasibility of mobile BIM PMIS based on cloud computing as a business model. In case of applying mobile BIM PMIS, 3D drawings and integrated building informations are possible on mobile devices in real time. it would support increasing the productivity of project participants as designer, engineer, supervisor, and etc. Globally, BIM based PMIS and Mobile BIM system, cloud computing based mobile BIM simulator are in the concept or experimental phase, therefore it is possible to secure global leading technology of IT and construction merger in the mobile BIM.

• 한국정보과학회논문지:시스템및이론
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• 제34권7호
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• pp.304-318
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• 2007

그리드(Grid) 컴퓨팅은 지리적으로 분산된 컴퓨팅 자원들을 네트워크로 연동시켜 서로 공유 될 수 있도록 해주는 서비스이다. 본 논문에서는 그리드 컴퓨팅 시스템을 구성하는 전체 노드를 대상으로 작업을 분배하는 메타 스케줄링 정책과 특정 한 개의 노드 내에서 작업을 분배하는 작업 스케줄링을 동시에 고려하는 하이브리드 스케줄링 기법을 제안한다. 그리드 컴퓨팅 노드로 제출된 작업을 필요 프로세서 수와 예상 작업수행 시간에 따라 구분하여 우선순위가 높은 작업은 작업 큐(Job Queue)로, 우선순위가 낮은 작업과 원거리 작업은 백필 큐(Backfill Queue)로 할당시킴으로써, 그리드 컴퓨팅 시스템의 성능을 높이는 방법을 연구한다. 다양한 실험을 통하여 제안된 기법들의 성능을 평가하며, 그리드 컴퓨팅 시스템의 이용률이 높아지고, 작업 지연시간이 감소됨을 확인한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.207-220
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• 2011

Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.

• 전자공학회논문지B
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• 제31B권7호
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• pp.149-158
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• 1994

Recently the fuzzy control is widely used as a tool for constructing automatic control systems which can replace the manual operation of large-scale nonlinear plants. In most applications of the fuzzy control however it is hard to meet the requirement of the operation time. In some real-time control the fuzzy control scheme requires too much computing time for fuzzification inference and defuzzification. To reduce the computing time there may be two alternatives the development of a new operation algorithm and the design of high-speed fuzzy hardware. In this paper to solve the problem of reducing the fuzzy operation time we propose a new high-speed fuzzy hardware scheme which has merits of its generality and extensibility. Finally we verify the proposed fuzzy hardware.

• 전자통신동향분석
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• 제35권4호
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• pp.34-41
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• 2020

The existing Von Neumann architecture places limits to data processing in AI, a booming technology. To address this issue, research is being conducted on computing architectures and artificial neural networks that simulate neurons and synapses, which are the hardware of the human brain. With high-speed, high-throughput data communication infrastructures, photonic solutions today are a mature industrial reality. In particular, due to the recent outstanding achievements of artificial neural networks, there is considerable interest in improving their speed and energy efficiency by exploiting photonic-based neuromorphic hardware instead of electronic-based hardware. This paper covers recent photonic neuromorphic studies and a classification of existing solutions (categorized into multilayer perceptrons, convolutional neural networks, spiking neural networks, and reservoir computing).

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.1-5
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• 1988

The realization of high quality robot control needs the improvement of computing speed of controller. In this paper, parallel processing method is considered for this purpose. A S/W algorithm for task scheduling is developed first, and then, an appropriate H/W structure is proposed. This scheme is applied to calculate inverse kinematics of PUMA robot. The simulation results show that the computing time when using three 8086/87's is reduced to 4.23 msec compared to 10 msec in case using one 8086/87.

• Journal of Advanced Marine Engineering and Technology
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• 제34권6호
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• pp.858-863
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• 2010

H.264/AVC를 이용한 동영상의 부호화에서 그 속도를 높이기 위해서는 움직임 예측시간을 줄이는 것이 매우 중요하다. 본 논문에서는 H.264/AVC 부호기의 오픈 소스인 x.264를 대상으로 움직임 예측 알고리즘을 CUDA 기반에서 구현함으로서 기존의 압축 기술 이상의 속도 향상 및 CPU의 점유율을 경감 시킬 수 있음을 검증한다.

• 전자공학회논문지B
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• 제32B권11호
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• pp.1527-1535
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• 1995

This paper introduces an isolated word recognition system realized on a neurocomputer called E-MIND II, which is a 2-D torus wavefront array processor consisting of 256 DNP IIs. The DNP II is an all digital VLSI unit processor for the EMIND II featuring the emulation capability of more than thousands of neurons, the 40 MHz clock speed, and the on-chip learning. Built by these PEs in 2-D toroidal mesh architecture, the E- MIND II can be accelerated over 2 Gcps computation speed. In this light, the advantages of the E-MIND II in its capability of computing speed, scalability, computer interface, and learning are especially suitable for real time application such as speech recognition. We show how to map a TDNN structure on this array and how to code the learning and recognition algorithms for a user independent isolated word recognition. Through hardware simulation, we show that recognition rate of this system is about 97% for 30 command words for a robot control.