• Journal of Korean Society of Industrial and Systems Engineering
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• v.43 no.3
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• pp.41-52
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• 2020

This paper investigates the stress-reducing preventive maintenance model through numerical experiments. The preventive maintenance model is used to analyze the relationship between related conditions and variables to gain insight into the efficient operation of the system when performing preventive maintenance in real-world situations. Various preventive maintenance models have been developed over the past decades and their complexity has increased in recent years. Increasing complexity is essential to reflect reality, but recent models can only be interpreted through numerical experiments. The stress-reducing preventive maintenance is a newly introduced preventive maintenance concept and can only be interpreted numerically due to its complexity, and has received little attention because the concept is unfamiliar. Therefore, for information purposes, this paper investigates the characteristics of the stress-reducing preventive maintenance and the relationship between parameters and variables through numerical experiments. In particular, this paper is focusing on the economic feasibility of stress-reducing preventive maintenance by observing changes in the optimal preventive maintenance period in response to changes in environmental stress and the improvement factor. As a result, when either the environmental stress or the improve effect of stress-reducing preventive maintenance is low, it is not necessary to carry out the stress-reducing preventive maintenance at excessive cost. In addition, it was found that the age reduction model is more economical than the failure rate reduction model.

• International Journal of Computer Science & Network Security
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• v.21 no.11
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• pp.312-320
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• 2021

Increase in computational cost and exhaustive search can lead to more complexity and computational energy. Thus, there is need for effective and efficient scheme to reduce the complexity to achieve optimal energy utilization. This will improve the energy efficiency and enhance the proficiency in terms of the resources needed to achieve convergence. This paper primarily focuses on the development of hybrid swarm intelligence scheme for reducing the computational complexity in binary optimization. In order to reduce the complexity, both artificial bee colony (ABC) and particle swarm optimization (PSO) have been employed to effectively minimize the exhaustive search and increase convergence. First, a new approach using ABC and PSO has been proposed and developed to solve the binary optimization problem. Second, the scout for good quality food sources is accomplished through the deployment of PSO in order to optimally search and explore the best source. Extensive experimental simulations conducted have demonstrate that the proposed scheme outperforms the ABC approaches for reducing complexity and energy consumption in terms of convergence, search and error minimization performance measures.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.4
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• pp.392-404
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• 2010

Recently, as both business processes and IT systems become ever more complex. Especially, enterprise applications tend to become unmanageably complex and increasingly costly to maintain. Therefore complexity is the insidious enemy of software development. It is critical to have a methodology that recognizes and manages this enemy effectively. In this paper, we propose ISIS (Integrated System of Independent Subsystems) - the architectural style needed to develop the complex enterprise applications. The ISIS was developed to meet the challenge of reducing the complexity of a larger enterprise application today. It gives us architecture models for reducing development complexity and composite application. The enterprise application is partitioned into a collection of independent subsystems using ISIS decomposition schemes and equivalence relations. We use middleware named ISIS engine that provides a service for subsystems interoperability by enabling the integration of distributed, cross-platform subsystems. We have implemented an ITSM system that achieves our objectives, reducing development complexity, using the ISIS architecture. Finally, ISIS architecture provides greater flexibility and productivity when an organization needs either to change its business processes, or to update the underlying systems.

• Nuclear Engineering and Technology
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• v.54 no.10
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• pp.3682-3694
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• 2022

The expansion of a country's ecological footprint generates resources for economic development. China's import bill and carbon footprint can be reduced by investing in green transportation and energy technologies. A sustainable environment depends on the cessation of climate change; the current study investigates nuclear energy efficiency, economic complexity, air transportation, and industrial improvement for reducing environmental footprint. Using data spanning the years 1983-2016, the dynamic autoregressive distributed lag simulation method has demonstrated the short- and long-term variability in the impact of regressors on the ecological footprint. The study findings revealed that economic complexity in China had been found to have a statistically significant impact on the country's ecological footprint. Moreover, the industrial improvement process is helpful for the ecological footprint in China. In the short term, air travel has a negative impact on the ecological footprint, but this effect diminishes over time. Additionally, energy innovation is negative and substantial both in the short and long run, thus demonstrating its positive role in reducing the ecological footprint. Policy implications can be extracted from a wide range of issues, including economic complexity, industrial improvement, air transportation, energy innovation, and ecological impact to achieve sustainable goals.

• Journal of applied mathematics & informatics
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• v.20 no.1_2
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• pp.637-645
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• 2006

An adaptive algorithm for reducing the hardware complexity is presented. This paper proposes a simplified LMS algorithm for the adaptive system and analyzes its convergence characteristics mathematically. An objective of the proposed algorithm is to reduce the hardware complexity. In order to test the performances, it is applied to the echo canceller, and a program is described. The results from simulations show that the echo canceller adopting the proposed algorithm achieves almost the same performances as one adopting the NLMS algorithm. If an echo canceller is implemented with this algorithm, its computation quantities are reduced to the half as many as the one that is implemented with the LMS algorithm, without so much degradation of performances.

• ETRI Journal
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• v.27 no.5
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• pp.639-642
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• 2005

This paper proposes two kinds of complexity-reduced algorithms for a low density parity check (LDPC) decoder. First, sequential decoding using a partial group is proposed. It has the same hardware complexity and requires a fewer number of iterations with little performance loss. The amount of performance loss can be determined by the designer, based on a tradeoff with the desired reduction in complexity. Second, an early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Once the edges are detected, no further iteration is required; thus early detection reduces the computational complexity.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.2
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• pp.485-499
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• 2021

Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.10
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• pp.5063-5073
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• 2016

In this paper, an efficient texture compression method is proposed for fast rendering, which exploits the spatial correlation among blocks through intra-picture block matching. Texture mapping is widely used to enhance the visual quality of results in real-time rendering applications. For fast texture mapping, it is necessary to identify an effective trade-off between compression efficiency and computational complexity. The conventional compression methods utilized for image processing (e.g., JPEG) provide high compression efficiency while resulting in high complexity. Thus, low complexity methods, such as ETC1, are often used in real-time rendering applications. Although these methods can achieve low complexity, the compression efficiency is still lower than that of JPEG. To solve this problem, we propose a texture compression method by reducing the spatial redundancy between blocks in order to achieve the better compression performance than ETC1 while maintaining complexity that is lower than that of JPEG. Experimental results show that the proposed method achieves better compression efficiency than ETC1, and the decoding time is significantly reduced compared to JPEG while similar to ETC1.

• Journal of the Society of Naval Architects of Korea
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• v.56 no.1
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• pp.1-10
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• 2019

Naval ship design and related other activities can be characterized by the complexity of the interactions among products, activities, and disciplines. Such complexities often result in inferior designs, cost overrun, and late-delivery. Hence there exist tremendous interests in both improving the design process itself and optimizing the interactions among design activities. This paper looks at the complexity of designing naval ships thereby leading to the innovation of current ship design practices using design structure matrix. It can be used to induce the optimal ordering of design activities as well as identify sources of complexities. The method presented here identifies coupled design activities useful for reducing the complexity of naval ship design as well as optimally reordering design activities. This paper recommends the use of design structure matrix method suitable for numerically optimizing the concept design process of naval ship, and reducing cost and time required in designing naval ships by modeling and analyzing the design activities and engineering tasks, defined in systems engineering planning documents.