• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.103-109
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• 2008

This paper presents the architecture and design of intra prediction circuit for H.264 decoder. There are a total of 17 operational modes in the intra prediction of H.264- nine modes for a luma $4\times4$ block, four modes for a luma $16\times16$ block and four modes for a chroma $8\times8$ block. We extracted common operations included in all prediction modes and defined the common operations unit to perform those operations. The proposed circuit architecture sharing this unit in all prediction modes is systematic from the design point of view and efficient in terms of circuit size.

• Convergence Security Journal
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• v.19 no.4
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• pp.13-22
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• 2019

The purpose of this study is to suggest the educational system and direction of cyber operations officers of non-cyber operations forces who do not specialize in cyber operations. In order to carry out cyber operations as a joint operation, non-Cyber Operations officers must also know about cyber operations, but there is no education system for them at present, Since there is almost no previous research on this, research in the relevant field is necessary. Therefore, the education system was developed based on the prior literature review, that is, the education system, that is, the necessity of education, the object of education, the goals and contents of the education, and the curriculum. In addition, the relevant experts confirmed the validity of each item with Delphi method, and as a result, some improvement was needed, but it was shown to be suitable as a whole. In addition, detailed educational program development can be developed based on this in the future.

• Advances in pediatric surgery
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• v.4 no.2
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• pp.110-116
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• 1998

This is a clinical review of 2,191 pediatric surgical patients under the age of 15 years, operated upon at the Division of Pediatric Surgery, Department of Surgery, Chonnam University Hospital from January 1988 to December 1997. The total number of operations in the pediatric age for all specialties were 13,144(13.2 %). The total operations including those performed on adults were 99,555. The most common age group operated upon was under 5 year of age(44.4 %). The number of operations in Division of General Pediatric Surgery were 2,191(16.7 %) out of total 13,144 operations in all pediatric specialties. The patients under 1 year of age in general pediatric surgery was 42.9 %(941/2,191). The most common diseases in neonates were anorectal malformation(20.6 %) and hypertrophic pyloric stenosis(20.3 %). Infants older than neonates most commonly were operated upon for inguinal hernia(32.4 %) and intussusception(19.6 %). The total mortality rate in the neonatal intensive care unit was 31.3 %. Gastroschisis had the highest mortality.

• Journal of the Korean Society of Systems Engineering
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• v.11 no.1
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• pp.73-79
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• 2015

This paper describes boundary analysis for modeling Aircraft Carrier Sortie Generation System(CVSGS). An aircraft carrier, as a super system, is a warship going into battle by operating a number of aircraft on deck and it should be lay down a definition about aviation operations interacting between aircraft carrier and carrier air wing in small deck area. For this reason this paper models common aviation support system for generating sortie basic unit of carrier aviation operations unlike to general warship and defines boundaries between this system and aircraft carrier and carrier air wing. This paper analysis activities of aircraft carrier and embarked carrier air wing in carrier aviation operations, and analysis and defines boundaries Aircraft Carrier Sortie Generation System(CVSGS) to perform core functions in interacting between aircraft carrier and embarked carrier air wing.

• Journal of the Korea Computer Industry Society
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• v.3 no.2
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• pp.149-158
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• 2002

This paper deals with design and verification of an arithmetic logic unit(ALU) to be used for development of optical computers. The ALU is based on optical switching device, $LiNbO_3$, which is easy to interface with electronic technology and most common in the market. It consists of an arithmetic/logic circuit performing logic operations, memory devices storing operands and the results of operations, and supplementary circuits to select instruction codes, and operates in bit-serial manner. In addition, a simulator is developed for verification of the design, and a set of basic instructions are executed in sequence and step-by-step changes in the accumulator and the memory are examined through simulations, to show that various operations are performed correctly.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.337-340
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• 2009

Since a hardware accelerator for 3D graphics processing GPU(Graphics Processing Unit)'s performance has been improving constantly. This is the efficient way was introduced for complex graphics application, but it is rarely used to utilize 100% resources on GPU. GP-GPU(general-purpose GPU), including operations on the GPU and supporting common operations can be handled by the processor, is noted by depending on the distribution of resources that can be effectively controlled. In this paper, the simulator was implemented that supports virtual environment of GP-GPU and available for program design and debugging. Through this, the co-design development environment support simultaneous design fast and reliable verification that are available to build the interface of three-dimensional graphics display.

• Journal of the Korean Operations Research and Management Science Society
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• v.20 no.1
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• pp.115-130
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• 1995

This paper considers a single machine nonpreemptive scheduling problem with a given common due date. In the problem, the optimal job sequence is sought to minimize the sum of earliness/tardiness and flow time measures in the situation where all jobs are available at time zero, and weights per unit length of earliness/tardiness and flow time are V and W, respectively. Some dominant solution properties are characterized to deriva both an optimal starting time for an arbitrary sequence and sequence improvement rules. The optimal schedule is found to the case W .geq. V/. By the way, it is difficult to find the optimal schedule for the case W < V. Therefore, the derived properties are put on together to construct a heuristic solution algorithm for the case W < V, and its effectiveness is rated at the mean relative error of about 3% on randomly generated numerical problems.

• Journal of Digestive Cancer Research
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• v.5 no.1
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• pp.37-43
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• 2017

Laparoscopic cholecystectomy is of one the most common general surgical operations performed today. Concomitant choledocholithiasis occurs in roughly 10-20% of patients with symptomatic gallstones. Laparoscopic bile duct exploration (LBDE) offers a single-stage minimally-invasive solution to the management of choledocholithiasis. LBDE may be performed either via the transcystic route or via laparoscopic choledochotomy. A number of strategies to improve success are available to the surgeon to help in the problem of complicated choledocholithiasis, these range from simple maneuvers to the use of laser or mechanical lithotriptors. With the advances in laparoscopic surgery, it is also possible to handle complex surgical conditions such as Mirizzi syndrome or recurrent pyogenic cholangitis laparoscopically, even though these have yet to be accepted as standard of care. Following laparoscopic choledochotomy, options for closure include: primary closure, closure over a T-tube, and closure over an endobiliary stent. T-tube placement has been associated with increased operating time and hospital length of stay compared to primary closure, with no significant differences in morbidity. Based on the available literature, LBDE appears comparable to ERCP with regards to procedural efficacy and morbidity. LBDE remains relevant to the general surgeon and is best viewed as being complementary to endoscopic therapy in the management of choledocholithiasis.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Safety and Health at Work
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• v.10 no.3
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• pp.347-354
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• 2019

Background: The aim of this study was to describe the types of diseases that developed in semiconductor workers who have registered with the Korea Workers' Compensation and Welfare Service (KWCWS) and to identify potential common occupational characteristics by the type of claimed disease. Methods: A total of 55 semiconductor workers with cancer or rare diseases who claimed to the KWCWS were compared based on their work characteristics and types of claimed diseases. Leukemia, non-Hodgkin lymphoma, and aplastic anemia were grouped into lymphohematopoietic (LHP) disorder. Results: Leukemia (n = 14) and breast cancer (n = 10) were the most common complaints, followed by brain cancer (n = 6), aplastic anemia (n = 6), and non-Hodgkin lymphoma (n = 4). LHP disorders (n = 24) accounted for 43%. Sixty percent (n = 33) of registered workers (n = 55) were found to have been employed before 2000. Seventy-six percent (n = 42) of registered workers and 79% (n = 19) among the registered workers with LHP (n = 24) were found to be diagnosed at a relatively young age, ${\leq}40years$. A total of 18 workers among the registered semiconductor workers were finally determined to deserve compensation for occupational disease by either the KWCWS (n = 10) or the administrative court (n = 8). Eleven fabrication workers who were compensated responded as having handled wafers smaller than eight inches in size. Eight among the 18 workers compensated (44 %) were found to have ever worked at etching operations. Conclusion: The distribution of cancer and rare diseases among registered semiconductor workers was closely related to the manufacturing era before 2005, ${\leq}8$ inches of wafer size handled, exposure to clean rooms of fabrication and chip assembly operations, and etching operations.