• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2014년도 추계학술대회
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• pp.10-11
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• 2014

In a 2-dimensional (2D) Discrete Cosine Transform (DCT) hardware, a significant fraction of the total hardware area is contributed by the combinational logic used to perform 1-dimensional (2D) transform. The size of the non-combinational logic i.e. the transpose memory is dictated by the size of the largest transform supported. Hence, the optimization of hardware area is performed mainly for 1D-transform combinational logic. This paper demonstrates the use of Multiple Constant Multiplication (MCM) algorithm to reduce the combinational logic area. Partial optimizations are also described for the cases where the direct use of MCM algorithm doesn't meet the timing constraint. Experimental results show that 46% improvement in gate count is achieved for 32 point 1D DCT transform logic after using MCM optimization.

• 전자공학회논문지C
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• 제35C권4호
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• pp.1-10
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• 1998

Partitioning problem of large combinational logic has been studied in real world. Most of logic include undectable faults from the structure of it's redundant, fan-out-reconvergent, and symetrical feature. BPT algorithm is proposed to enhance the fault voverage for combinational logic partitioning. This algorithm partitions the logic by cut the lines related to undetectable structure when seperating. Controllability and observability are considered in the process of partitioning. This algorithm is evaluated effective by testing ISCAS85 circuits.

• 대한전자공학회논문지
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• 제13권3호
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• pp.1-6
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• 1976

이 논문에서는 Boolean difference를 이용하여 combinational 및 sequential 논리회로에서 발생하는 기능적인 고장에 대한 test pattern을 얻는 방법을 연구하였다. 이 방법은 test pattern을 얻고자 하는 회로의 Boolean 함수의 Boolean difference를 계산하므로써 체계적으로 test pattern을 얻는 절차를 보여주고 있다. 컴퓨터에 의한 실험결과에 의하며 이 방법은 combinational 회로 및 asynchronous sequential 회로에 적합하며, clock이 있는 flip flop을 적당히 모형화함으로서 이 방법을 synchronous sequential회로에도 적용할 수 있음이 입증되었다. In this paper, a method of test pattern generation for the functional failure in both combinational and sequentlal logic networks by using exterded Boole an difference is proposed. The proposed technique provides a systematic approach for the test pattern generation procedure by computing Boolean difference of the Boolean function that represents the Logic network for which the test patterns are to be generated. The computer experimental results show that the proposed method is suitable for both combinational and asynchronous sequential logic networks. Suitable models of clocked flip flops may make it possible for one to extend this method to synchronous sequential logic networks.

• 한국통신학회논문지
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• 제14권5호
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• pp.503-510
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• 1989

본 논문에서는 조합 다치논리 회로를 구성하는 이론을 제시하였다. 먼저 조합 다치논리 회로구성은 입력되는 변수를 기준으로 하여 셀을 구성한 후 이를 확장하여 일반적인 경우에 까지 적용하도록 하였으므로 구성절차가 단순하고 규칙적이다. 본 논문에서 제시한 다치논리 회로구성이론은 규칙성, 간단성, 모듈성의 특징을 가지며, 특히 다치논리 회로에 입력되는 변수가 증가되는 경우 다치논리 회로 구성은 확장성을 갖는다.

• 전자공학회논문지C
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• 제34C권11호
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• pp.12-19
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• 1997

In this paper, we present a logic synthesis algorithm for low powr design fo combinational circuits. The proposed algorithm reduces power dissipation by eliminating unnecessary signal transitions. The proposed algorithm restructures a given circuit by using a kernel as prediction logic in a precomputation-based scheme such that switching activity of circuit can be minimized. Experimental results show that the system is efficient for low power design of combinational circuits.

• 전자공학회논문지A
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• 제30A권9호
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• pp.71-79
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• 1993

This paper proposes a new test pattern generation methodology for combinational logic circuits using neural networks based on a modular structure. The CUT (Circuit Under Test) is described in our gate level hardware description language. By conferring neural database, the CUT is compiled to an ATPG (Automatic Test Pattern Generation) neural network. Each logic gate in CUT is represented as a discrete Hopfield network. Such a neual network is called a gate module in this paper. All the gate modules for a CUT form an ATPG neural network by connecting each module through message passing paths by which the states of modules are transferred to their adjacent modules. A fault is injected by setting the activation values of some neurons at given values and by invalidating connections between some gate modules. A test pattern for an injected fault is obtained when all gate modules in the ATPG neural network are stabilized through evolution and mutual interactions. The proposed methodology is efficient for test generation, known to be NP-complete, through its massive paralelism. Some results on combinational logic circuits confirm the feasibility of the proposed methodology.

• 한국정보통신학회논문지
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• 제9권6호
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• pp.1288-1293
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• 2005

본 논문에서는 TDBM과 CMTEDD를 사용하여 다중출력조합디지털논리시스템 설계방법의 한가지를 제안하였다. 또한, CBDD와 CMTEDD를 기반으로 최종 조합디지털논리시스템 구성을 멀티플렉서를 사용하여 구현하였다. 제안한 방법은 기존의 방법에 비해 모듈사이의 내부결선을 효과적으로 줄일 수 있으며 입력변수의 쌍과 출력함수의 쌍에 의해 게이트 수를 줄일 수 있는 장점이 있다.

• 한국정보처리학회논문지
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• 제3권3호
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• pp.564-571
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• 1996

본 논문에서는 새로운 ASIC 구조로 최근에 관심을 모으고 있는 TLU형 FPGA를 위한 순차회로 기술 매핑에 관한 것이다. 본 고에서 제안하는 TLU형 FPGA를 위한 순차회로 기술 매핑방법은 먼저 6개 또는 7개의입력을가지는 조합 및 순차 노드에대해서 전처리 기를 사용하여 한 출력 CLB에매핑하고, 매핑안된나머지 중 순차회로합병 조건에 만족 하는 6개 혹은 7개 입력 변수를 갖는 노드부터 CLB에 매핑한다. 본 고에서 제안한 순차 회로 기술 매핑 방법이 간단하면서 만족스런 수행 시간과 결과를 얻었다. 여러개의 벤치마크 화로를 sis-pga(map_together 및 map_scparate)순차회로 합성 시스템과 비교 하였으며, 실험결과는 본 시스템이 sis-pga 보다 17% 이상 성능이 좋다는 결과를 보여 주고 있다.

• 대한전자공학회논문지
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• 제14권6호
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• pp.10-15
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• 1977

This paper proposes a simple and systematic method for the generation of the fault detection test sets for the combinational logic networks. Based on tile path sensitizing concept, the test patterns for the primary input gates of the network are defined, and then it is shown that, arranging these predefined test patterns according to the path sensitizing characteristics of the given network sturctures, the minimal complete test sets for the fan-out free combinational networks can be found easily. It is also shown that, taking into account the fan-out paths sensitizing compatibility, the proposed method can be extended to the irredundant reconvergent fan-out networks.

• 전자공학회논문지A
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• 제31A권4호
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• pp.106-115
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• 1994

This paper presents the design of a technology mapping system for optimizing delays of combinational and synchronous sequential logic circuits. The proposed system performs delay optimization for combinational logic circuits by remapping, buffering, and gate merging methods through the correct delay calculation in which the loading values are considered. To get time optimized synchronous sequential circuits, heuristic algorithms are proposed. The proposed algorithms reallocate registers by considering the critical path characteristics. Experimental results show that the proposed system produces a more optimized technology mapping for MCNC benchmarks compared with mis-II.