• Title/Summary/Keyword: coded block pattern

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Fast Intermode Decision Method Using CBP on Variable Block Coding (가변 블록 부호화에서 CBP를 이용한 고속 인터모드 결정 방법)

  • Ryu, Kwon-Yeol
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.7
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    • pp.1589-1596
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    • 2010
  • In this paper, we propose the method that reduce computational complexity for intermode decision using CBP(coded block pattern) and coded information of colocated-MB(macro block). Proposed method classifies MB into best-CBP and normal-CBP according to the characteristics of CBP. On best-CBP, it eliminates the computation for $8{\times}8$ mode on intermode decision process because the probability for SKIP mode and M-Type mode is 96.3% statistically. On normal-CBP, it selectively eliminates the amount of computation for bit-rate distortion cost, because it uses coded information of colocated-MB and motion vector cost in deciding SKIP mode and M-Type mode. The simulation results show that the proposed method reduces total coding time to 58.44% in average, and is effective in reducing computational burden in videos with little motion.

An MPEG2-to-H.264 Transcoding Method (MPEG2에서 H.264로의 트랜스코딩 기법)

  • Kim, Dong-Hyung;Jeong, Je-Chang
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.7C
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    • pp.706-715
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    • 2005
  • In this paper, we present a transcoding algorithm for converting an MPEG-2 video bitstream to an H.264 bitstream. The proposed transcoder consists of two parts. One is MPEG2 decoding part and the other is H.264 encoding part Because our algorithm is for transcoding in the spatial domain, MPEG2 decoding part carries out full decoding of MPEG2 bitstream. While, because macroblock type and coded block pattern in MPEG2 are significantly related to macroblock mode in H.264, macroblock mode is selected adaptively according to macroblock type and coded block pattern in H.264 decoding part. Furthermore, motion vector is also used as side-information for 16$\ctimes$16 macroblock mode. Simulation results show that the proposed transcoder yields high reduction of total transcoding time at comparable PSNR.

A Fast Block Matching Motion Estimation Algorithm by using an Enhanced Cross-Flat Hexagon Search Pattern (개선된 크로스-납작한 육각 탐색 패턴을 이용한 고속 블록 정합 움직임 예측 알고리즘)

  • Nam, Hyeon-Woo
    • Journal of the Korea Society of Computer and Information
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    • v.13 no.7
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    • pp.99-108
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    • 2008
  • For video compression, we have to consider two performance factors that are the search speed and coded video's quality. In this paper, we propose an enhanced fast block matching algorithm using the spatial correlation of the video sequence and the center-biased characteristic of motion vectors(MV). The proposed algorithm first finds a predicted motion vector from the adjacent macro blocks of the current frame and determines an exact motion vector using the cross pattern and a flat hexagon search pattern. From the performance evaluations, we can see that our algorithm outperforms both the hexagon-based search(HEXBS) and the cross-hexagon search(CHS) algorithms in terms of the search speed and coded video's quality. Using our algorithm, we can improve the search speed by up to 31%, and also increase the PSNR(Peak Signal Noise Ratio) by at most 0.5 dB, thereby improving the video quality.

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A Research on dissolve detection in MPEG video streams using coded block pattern (MPEG 동영상에서 부호화된 블록의 개수를 이용한 점진적 장면 전환 영역 검출)

  • 남승필;오화종;최병욱
    • Proceedings of the IEEK Conference
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    • 2000.09a
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    • pp.733-736
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    • 2000
  • 멀티미디어 데이터베이스에서 장면전환 영역을 검출하는 것은 검색과 색인을 위해서 필수적이다. 동영상에서 장면전환 영역은 단순한 장면전환과 점진적인 장면전환으로 나눌 수 있다. 단순한 장면전환은 다음 장면과 구별이 쉬우나, 점진적인 장면전환은 그 구별이 쉽지 않다. 본 논문에서는 압축된 동영상에서 점진적인 장면전환 영역을 검출하는 효과적인 방법을 제시한다. 제안된 알고리즘은 MPEG-1으로 압축된 동영상에서 DC계수를 추출하고, 부호화된 휘도 블럭의 개수를 추출하여 점진적 장면전환 영역을 검출한다. 제안된 알고리즘의 성능은 장면이 점진적으로 바뀌는 영역을 찾아내는 정확도를 기반으로 분석하였다.

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A Fast Inter Mode Decision Algorithm Considering Quantization Parameter in H.264 (H.264 표준에서 양자화 계수를 고려한 고속 인터모드 결정 방법)

  • Kim, Geun-Yong;Ho, Yo-Sung
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.43 no.6 s.312
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    • pp.11-19
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    • 2006
  • The recent video coding standard H.264 employs the rate-distortion optimization (RDO) method for choosing the best coding mode; however, it causes a large amount of encoding time. Thus, in order to reduce the encoding time, we need a fast mode decision algorithm. In this paper, we propose a fast inter mode decision algorithm considering quantization parameter (QP). The occurrence of best modes depends on QP. In order to reflect these characteristics, we consider the coded block pattern (CBP) which has 0 value when all quantized discrete cosine transform (DCT) coefficients are zero. We also use the early SKIP mode decision and early $16{\times}16$ mode decision methods. By computer simulations, we have verified that the proposed algorithm requires less encoding time than the fast inter mode decision method of the H.264 reference software for the Baseline and Main profiles by 19.6% and 18.8%, respectively.

A Fast Block Matching Motion Estimation Algorithm by using the Enhanced Cross-Hexagonal Search Pattern (개선된 크로스-육각 패턴을 이용한 고속 블록 정합 움직임 추정 알고리즘)

  • Nam Hyeon-Woo
    • Journal of the Korea Society of Computer and Information
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    • v.11 no.4 s.42
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    • pp.77-85
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    • 2006
  • There is the spatial correlation of the video sequence between the motion vector of current blocks. In this paper, we propose the enhanced fast block matching algorithm using the spatial correlation of the video sequence and the center-biased properly of motion vectors. The proposed algorithm determines an exact motion vector using the predicted motion vector from the adjacent macro blocks of the current frame and the Cross-Hexagonal search pattern. From the of experimental results, we can see that our proposed algorithm outperforms both the prediction search algorithm (NNS) and the fast block matching algorithm (CHS) in terms of the search speed and the coded video's quality. Using our algorithm, we can improve the search speed by up to $0.1{\sim}38%$ and also diminish the PSNR (Peak Signal Noise Ratio) by at nst $0.05{\sim}2.5dB$, thereby improving the video qualify.

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Reduction of Blocking Effect using a Rational Open Uniform B-Spline Curve (유리 개방형 균일 B 스플라인 곡선을 이용한 블록 효과 감소)

  • 김희정;김지홍
    • Journal of Korea Multimedia Society
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    • v.5 no.4
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    • pp.386-392
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    • 2002
  • In this paper, we propose a novel blocking effect reduction method based on a rational B-spline. The blocking effect results from independent coding of each image block and becomes highly visible especially coded at very low bit rates. The proposed approach adopts a rational open uniform B-spline curve that used to produce a smooth curve through a set of control points. The pixels on the block boundary are treated as control points, and the weight values, which decide the shape of curve, are determined differentially by considering the distance the position of the pixels and that of the block boundary. The simulation results show that the proposed method has excellent performance for all pattern of the blocking effect with less computational complexity.

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Circuit Design of a Blocking Effect Reduction Algorithm using B-Spline Curve (스플라인 곡선을 이용한 블록화 현상 감소 회로의 설계)

  • 박성모;김희정;최진호;김지홍
    • Journal of Korea Multimedia Society
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    • v.6 no.7
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    • pp.1169-1177
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    • 2003
  • The blocking effect results from independent coding of each image block and becomes highly visible, especially coded at very low bit rates. In this paper, a blocking effect reduction circuit is designed which is composed of a memory, arithmetic and logic unit, and control block. The circuit is based on a rational open uniform B-spline curve that uses to produce a smooth curve through a set of control points. The weight values and the modified pixel values in a rational open uniform B-spline curve are calculated using arithmetic and logic circuits. The simulation results show that the circuit has excellent performance for ail pattern of the blocking effects.

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Efficient Entropy Coding Method for Scalable Video Coding (스케일러블 비디오 부호화를 위한 효율적인 엔트로피 부호화 방법)

  • Choi, Hyo-Min;Nam, Jung-Hak;Sim, Dong-Gyu;Choi, Byeong-Doo;Cho, Dae-Sung
    • Journal of Broadcast Engineering
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    • v.15 no.5
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    • pp.653-664
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    • 2010
  • Generally existing video codec employs entropy coding to deal with residual signals with considering temporal and spatial properties. Scalable Video Coding(SVC) which is extension of H.264/AVC has three technical concepts for removing redundancies between inter-layers. In spite of using novel prediction method between inter-layers in SVC, it is still using same entropy coding method to residual signals. According to the studies, the residual obtained by inter-layer prediction technique has different features of residual signal acquired by spatial or temporal prediction technique. In this paper, we propose an efficient entropy coding method which codes the residual signal obtained by inter-layer prediction with regarding its features adequately. We re-designed the Coded Block Pattern(CBP) table suitably for inter-layer texture prediction. The experiments show that the proposed method can further reduce the BD-Bitrate up to average 2.20% in 4CIF and 1.14% in CIF resolution compared to the existing JSVM 9.18.

An Efficient Architecture of Transform & Quantization Module in MPEG-4 Video Code (MPEG-4 영상코덱에서 DCTQ module의 효율적인 구조)

  • 서기범;윤동원
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.11
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    • pp.29-36
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    • 2003
  • In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.