• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.41 no.6
• /
• pp.253-260
• /
• 2004

This paper proposes a novel algorithm for hybrid lossless audio coding, which employs an integer wavelet transform and a linear prediction model. The proposed algorithm divides the input signal into flames of a proper length, decorrelates the framed data using the integer wavelet transform and linear prediction and finally entropy-codes the frame data. In particular, the adaptive Golomb-Rice coding method used for the entropy coding selects an optimal option which gives the best compression efficiency. Since the proposed algorithm uses integer operations, it significantly improves the computation speed in comparison with an algorithm using real or floating-point operations. When the coding algorithm is implemented in hardware, the system complexity as well as the power consumption is remarkably reduced. Finally, because each frame is independently coded and is byte-aligned with respect to the frame header, it is convenient to move, search, and edit the coded, compressed data.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1A
• /
• pp.31-36
• /
• 2004

In this paper, we proposed the new structure of the Rake Finger using Walsh Switch, the shared accumulator, and the pipeline-FWHT algorithm for reducing the signal processing complexity resulting from the increase of the number of data correlator. The function simulation of the proposed architecture is performed by Synopsys tool and the timing simulation is performed by Compass tool. The number of computational operation in the proposed data correlators is 160 additions and the conventional ones is 512 additions when the number of walsh code N=4. As a result, it is reduced about 3.2 times other than the number of computational operation of the conventional ones. Also, the result shows that the data processing time of the proposed Rake Finger architecture is 90,496[ns] and the conventional ones is 110,696[ns]. It is $18.3\%$ faster than the data processing time of the conventional Rake Finger architecture.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.8A
• /
• pp.1218-1226
• /
• 1999

In decoding the turbo codes, the sliding window BCJR algorthm, derived from the BCJR algorithm, permits a continuous decoding of the coded sequence without requiring trellis fermination of the constituent codes and uses reduced memory span. However, the number of computation required is greater than that of BCJR algorithm and no study on the effect of the window length has been reported. In this paper, we propose an eddicient sliding window type scheme which maintains the advantages of the conventional sliding window algorithm, reduces its computational burdens, and improves is BER performance. A guideline is first presented to determine the proper window length and then a computationally efficient sliding window BCJR algorithm is obtained by allowing the window to be forwarded in multi-step. Simulation results show that the proposed scheme outperforms the conventional sliding window BCJR algorithm with reduced complexity. It gains 0.1dB SNR improvements over the conventional method for the constraint length 3 and BER $10^{-4}$

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.11
• /
• pp.48-55
• /
• 2009

This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-${\mu}m$ CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300MHz and has a throughput of 115-Gb/s for 0.13-${\mu}m$ CMOS technology. As a result, the proposed three-parallel RS-FEC architecture has a much higher data processing rate and low hardware complexity compared with the conventional two-parallel, three-parallel and serial RS-FEC architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.5
• /
• pp.31-40
• /
• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

• Journal of Radiation Protection and Research
• /
• v.23 no.1
• /
• pp.1-6
• /
• 1998

A diffusion model of radioactive liquid effluents is developed and applied for YGN NPP's site, based on the Gaussian plume type model. Due to the complexity of oceanic diffusion characteristics of YGN site, a simple and reliable statistical model based on Reg. Guide 1.113 is developed. Also, a computer code package to calculate dilution factors as a function of plant operation conditions and pathway of radioactive materials. A liquid effluents diffusion model is developed by dividing the diffusion range into two categories, i. e, a near field mixing region and a far field mixing region. In the near field, the initial mixing is affected by a buoyance force, a high initial turbulence and momentum which is characterized by a plant operation condition and environmental conditions. The far field mixing is similar to gaseous effluents diffusion. So, beyond the near field region, wellknown Gaussian plume model was adopted. A different area averages of Gaussian plume equation was taken for each radioactive exposure pathway. As a result, we can get different dilution factors for different pathways. Results shows that present dilution factors used for YGN ODCM is too much overestimated compared with dilution factors calculated with the developed model.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.4
• /
• pp.12-19
• /
• 2016

The monitoring system in railway is under study to forecast any derailment and accident by defect of train. Because the monitoring system is composed of wireless sensor network based on ZigBee-communication between inside and outside of train, the study for wireless channel analysis is required. Especially, if multipath delay profile exist in the channel, the equalizer and channel estimator can be required for preventing receiver performance degradation. Therefore, we analyzed the wireless channel in train environment using measured data and, proposed the channel estimation method through the characterisitic of chip code, under the consideration of the channel characteristics in train. To show the performance of proposed method, we demonstrate the performance by mean square error(MSE), computational complexity and bit error rate(BER).

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.6
• /
• pp.459-468
• /
• 2003

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.6
• /
• pp.800-807
• /
• 2016

We propose a fast algorithm using Extreme Contour Point (ECP) to detect the angle of rotated images, is implemented by rotation feature of one covered frame image that can be applied to correct the rotated images like in image processing for real time applications, while CORDIC is inefficient to calculate various points like high definition image since it is only possible to detect rotated angle between one point and the other point. The two advantages of this algorithm, namely compatibility to images in preprocessing by using Sobel edge process for pattern recognition. While the other one is its simplicity for rotated angle detection with cyclic shift of two $1{\times}n$ matrix set without complexity in calculation compared with CORDIC algorithm. In ECP, the edge features of the sample image of gray scale were determined using the Sobel Edge Process. Then, it was subjected to binary code conversion of 0 or 1 with circular boundary to constitute the rotation in invariant conditions. The results were extracted to extreme points of the binary image. Its components expressed not just only the features of angle ${\theta}$ but also the square of radius $r^2$ from the origin of the image. The detected angle of this algorithm is limited only to an angle below 10 degrees but it is appropriate for real time application because it can process a 200 degree with an assumption 20 frames per second. ECP algorithm has an O ($n^2$) in Big O notation that improves the execution time about 7 times the performance if CORDIC algorithm is used.

• Proceedings of the KIEE Conference
• /
• 2008.07a
• /
• pp.936-937
• /
• 2008

As a micro computer or micro processor technology has been advanced, the essential part which consists of electric power system has been changed into intelligent electronic device(IED), that is one kind of embedded system. There are already many parts changed into digital from analog in control and maintenance devices of electric system. These trends make advanced and novel concepts of devices and systems, that we couldn't even imagine in the analog circumstances. Now, the rate's of change is comparatively slower than IT field that is mainly represented by mobile communication, but that is a big change in the history of electric industries. Some people in those field called it Power-IT, and there have been many kinds of researches. Accelerated systems to go digital, users always and continuously demand more convenient, practical, and new functions. So, a lot of electric system manufactures have had tasks realizing many kinds of functions in an electronic device. According to the high-end technologies in semi-conductor and micro-computer field, manufactures can fully satisfy almost all of customer's needs, but there are other kinds of problems, such as large amount of program code, increasing complexity in proportion with program amount, and the hardness of maintenance and revision of the program. So nowadays, the necessity of embedded OS was emerged as a solution, and many researchers and manufactures have concentrated on studies related to embedded OS and its application.