• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.1
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• pp.38-46
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• 2012

In this paper, we propose a decision feedback equalizer based on LDPC(Low Density Parity Check) code for the fast processing and performance improvement in OFDM system. LDPC code has good error correcting capability and its performance approaches the Shannon capacity limit. However, it has longer parity check matrix and needs more iteration numbers. In our proposed system, MSE(Mean Square Error) of signal between decision device and decoder is fed back to equalizer. This proposed system can improve BER performance because it corrects estimated channel response more accurately. In addition, the proposed system can reduce complexity because it has a lower number of iterations than system without feedback at the same performance. Simulation results evaluate and show the performance of OFDM system with the CFO and phase noise in multipath channel.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.2
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• pp.62-67
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• 2001

In the recent mobile communication systems, the performance of Turbo Code using the error correction coding depends on the interleaver influencing the free distance determination and the recursive decoding algorithms that is executed in the turbo decoder. However, performance depends on the interleaver depth that need a large time delay over the reception process. Moreover, Turbo Code has been known as the robust ending method with the confidence over the fading channel. The International Telecommunication Union(ITU) has recently adopted as the standardization of the channel coding over the third generation mobile communications such as IMT-2000. Therefore, in this paper, we proposed of the method to improve the conventional performance with the parallel concatenated 4-New Turbo Decoder using MAP a1gorithm in spite of complexity increasement. In the real-time video and video service over the third generation mobile communications, the performance of the proposed method was analyzed by the reduced decoding delay using the variable decoding method by computer simulation over AWGN and fading channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2A
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• pp.157-165
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• 2004

The synchronization algorithm of IEEE 802.11a WLAN(Wireless Local Area Network) has three consecutive processes, which use a short code training symbol, a long code training symbol and a pilot symbol respectively. But in using this synchronization processes, the actual embodiment has two problems. First, the synchronization process has the complex structure using a long code training symbol and a pilot symbol. Second, since the long training symbol is only compensated with the offset correction coefficient, it can not be trusted perfectly. If the equalizer coefficient is obtained in this unstable period, the system performance is degraded. In particular, the system performance becomes worst in case of the 54 Mbps transmission system using the maximum length of data. In this paper, the new algorithm is proposed which can resolve the embodiment complexity of synchronization processes and structural defect, and also it is confirmed by simulation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.5
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• pp.1316-1332
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• 2012

Formation flying is an important technology that enables high cost-effective organization of outer space aircrafts. The ad-hoc wireless network based on direct-sequence ultra-wideband (DS-UWB) techniques is seen as an effective means of establishing wireless communication links between aircrafts. In this paper, based on the theory of matched filter and error bits correction, a hybrid detection algorithm is proposed for realizing multiuser detection (MUD) when the DS-UWB technique is used in the ad-hoc wireless network. The matched filter is used to generate a candidate code set which may contain several error bits. The error bits are then recognized and corrected by an novel error-bit corrector, which consists of two steps: code mapping and clustering. In the former step, based on the modified optimum MUD decision function, a novel mapping function is presented that maps the output candidate codes into a feature space for differentiating the right and wrong codes. In the latter step, the codes are clustered into the right and wrong sets by using the K-means clustering approach. Additionally, in order to prevent some right codes being wrongly classified, a sign judgment method is proposed that reduces the bit error rate (BER) of the system. Compared with the traditional detection approaches, e.g., matched filter, minimum mean square error (MMSE) and decorrelation receiver (DEC), the proposed algorithm can considerably improve the BER performance of the system because of its high probability of recognizing wrong codes. Simulation results show that the proposed algorithm can almost achieve the BER performance of the optimum MUD (OMD). Furthermore, compared with OMD, the proposed algorithm has lower computational complexity, and its BER performance is less sensitive to the number of users.

• International Journal of Naval Architecture and Ocean Engineering
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• v.3 no.1
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• pp.27-36
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• 2011

In the proposed paper numerical calculations are carried out using two versions of a three-dimensional, timedomain panel method developed by the group of Prof. P. Sclavounos at MIT, i.e. the linear code SWAN2, enabling optionally the use of the instantaneous non-linear Froude-Krylov and hydrostatic forces and the fully non-linear SWAN4. The analytical results are compared with experimental results for three hull forms with increasing geometrical complexity, the Series 60, a reefer vessel with stern bulb and a modern fast ROPAX hull form with hollow bottom in the stern region. The details of the geometrical modeling of the hull forms are discussed. In addition, since SWAN4 does not support transom sterns, only the two versions of SWAN2 were evaluated over experimental results for the parent hull form of the NTUA double-chine, wide-transom, high-speed monohull series. The effect of speed on the numerical predictions was investigated. It is concluded that both versions of SWAN2 the linear and the one with the non-linear Froude-Krylov and hydrostatic forces provide a more robust tool for prediction of the dynamic response of the vessels than the non-linear SWAN4 code. In general, their results are close to what was expected on the basis of experience. Furthermore, the use of the option of non-linear Froude-Krylov and hydrostatic forces is beneficial for the accuracy of the predictions. The content of the paper is based on the Diploma thesis of the second author, supervised by the first one and further refined by the third one.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.289-293
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• 2000

We propose two new algorithms for parallelism-independent scheduling. The machine code generated from the compiler using these algorithms in its scheduling phase is parallelism-independent code, executable in minimum time regardless of the number of the processors in the parallel computer. Our new algorithms have the following phases: finding the minimum number of processors on which the program can be executed in minimal time, scheduling by an heuristic algorithm for this predefined number of processors, and serialization of the parallel schedule according to the earliest start time of the tasks. At run time tasks are taken from the serialized schedule and assigned to the processor which allows the earliest start time of the task. The order of the tasks decided at compile time is not changed at run time regardless of the number of the available processors which means there is no out-of-order issue and execution. The scheduling is done predominantly at compile time and dynamic scheduling is minimized and diminished to allocation of the tasks to the processors. We evaluate the proposed algorithms by comparing them in terms of schedule length to the CP/MISF algorithm. For performance evaluation we use both randomly generated DAGs (directed acyclic graphs) and DACs representing real applications. From practical point of view, the algorithms we propose can be successfully used for scheduling programs for in-order superscalar processors and shared memory multiprocessor systems. Superscalar processors with any number of functional units can execute the parallelism-independent code in minimum time without necessity for dynamic scheduling and out-of-order issue hardware. This means that the use of our algorithms will lead to reducing the complexity of the hardware of the processors and the run-time overhead related to the dynamic scheduling.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.3
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• pp.193-199
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• 2009

Powerline communications (PLC) technology has been discussed and analyzed as a highly potential candidate of wireline access network solutions. In this paper, performance of double binary turbo coded orthogonal frequency division multiplexing (OFDM) system is analyzed and simulated in power line communications channel. In order to make power line channel environments, Bernoulli-Gaussian noise is considered. The performance is evaluated in terms of bit error probability. From the simulation results, it is demonstrated that the double binary turbo coding scheme offers considerable coding gain with reasonable encoding complexity. It is also shown that the system performance can be substantially improved by increasing the number of iterations.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.5
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• pp.25-32
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• 2007

This paper proposes a distributed space-frequency block code (SFBC) for relay-assisted single carrier frequency-domain equalization (SC-FDE). The proposed technique achieves spatial diversity gain over fast fading channels without the complexity of multiple antennas. The mobile equipment of the proposed system has a very simple transmitter structure with constant amplitude transmit sequences, which is desirable especially for uplink communications. In order to obtain spatial diversity, the transmit sequence of relay is efficiently generated in the time domain, which is equivalent to the SFBC. Further, efficient implementation of relay and destination structures is also presented. Extensive simulation results show that the proposed system significantly outperforms the distributed space-time block code (D-STBC) SC-FDE over fast fading channels.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.13-19
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• 2008

In this paper, we propose a new CL-OSTBC (Closed Loop Orthogonal Space-Time Block Code) scheme for four transmit antennas and compare the scheme with existing closed loop schemes on the performance of BER (Bit Error Rate). In the proposed scheme, a transmitter receives channel feedback information and combines modulated symbols by the symbol combiner, and transmits the symbols encoded by the space-time block encoder. As a result, the proposed scheme achieves full-rate and maximal channel gains by more efficient utilization of the channel feedback information. Moreover, the scheme can reduce computation complexity by using a linear detector. Simulation results on the BER performance show that the proposed CL-OSTBC scheme outperforms existing CL-OSTBC schemes.

• Journal of the Korea Society of Computer and Information
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• v.12 no.1 s.45
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• pp.155-160
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• 2007

Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc.. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.