• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.51-58
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• 2013

A clock duty-cycle corrector (DCC) which is an essential device of clocking circuits for high-speed system-on-chip (SoC) design is introduced in this paper. The architectures and operation of conventional analog feedback DCCs and digital feedback DCCs are compared and analyzed. A new mixed-mode feedback DCC that combines the advantages of analog DCCs and digital DCCs to achieve a wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy is presented. Especially, the architectures and design of a mixed-mode duty-cycle amplifier (DCA) which is a core unit circuit of a mixed-mode DCC is presented in detail. Two mixed-mode DCCs based on a single-stage DCA and a two-stage DCA were designed in a 0.18-${\mu}m$ CMOS process, and it is proven that the two-stage DCA-based DCC has a wider duty-cycler correction range and smaller duty-cycle correction error.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.711-714
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• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.1-8
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• 2008

Low Density Parity Check codes(LDPC) are recently focused on communication systems due to its good performance. The standard of WiBro has also included LDPC codes as a channel coding. The weak point of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which limit throughput. In this paper, we propose semi-parallel architecture by using cyclic shift registers and exclusive-OR without conventional Matrix Vector Multipliers over the standard parity check matrices with Circulant Permutation Matrices(CPM). Furthermore, multi-rate encoder is designed by using proposed architecture. Our encoder with multi-rate for IEEE 802.16e LDPC has lower clock cycles and higher throughput.

• Proceedings of the Korean Society of Embryo Transfer Conference
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• 2006.10a
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• pp.59-59
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• 2006

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.465-466
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• 2006

In this paper, novel analog duty cycle corrector (DCC) with a digital duty error detector is proposed. The digital duty error detector measures the duty error of the clock and converts it into a digital code. This digital code is then used to accurately correct the duty ratio by adaptively steering the charge-pump current. The proposed duty cycle corrector was implemented using an 80nm DRAM process with 1.8V supply voltage. The simulation result shows that the proposed duty cycle corrector improves the settling time up to $70{\sim}80%$ at 500MHz clock frequency for the same duty correction accuracy as the conventional analog DCC.

• Journal of Photoscience
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• v.9 no.2
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• pp.240-242
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• 2002

In Drosophila melanogaster, it is known that the circadian clock consists of an autoregulatory feedback loop, which includes so-called clock genes, such as per, tim, dClk and cyc and produces periodical expression of per. It is recently suggested, however, that the circadian oscillation without the rhythmical expression of per is involved in the regulation of circadian locomotor rhythms. In the present study, we examined the existence and the property of the possible per-less oscillation using arrhythmic clock mutant flies carrying per$^{01}$, tim$^{01}$, dClk$^{Jrk}$ or cyc$^{01}$. When temperature cycles consisting of 25$^{\circ}$Ｃ and 30$^{\circ}$Ｃ with varying periods (T = 8~32 hr) were given, they showed rhythms synchronizing with the given cycle under constant darkness (DD). per$^{01}$ and tim$^{01}$ flies always showed a peak around 7 hr after the onset of thermophase irrespective of Ts of temperature cycles, while dClk$^{Jrk}$ and cyc$^{01}$ flies did not. In addition, several days were necessary to establish a clear temperature entrainment in per$^{01}$ and tim$^{01}$ flies, when they were transferred from a constant temperature to a temperature cycle under DD. These results suggest that per$^{01}$ and tim$^{01}$ flies have a temperature-entrainable weak oscillatory mechanism. The fact that dClk$^{Jrk}$ and cyc$^{01}$ flies did not show any sign of the endogenous oscillation suggests that the per-less oscillatory mechanism may require CLK and CYC.

• Journal of Electrical Engineering and Technology
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• v.8 no.4
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• pp.773-779
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• 2013

We propose an efficient method to measure a pulse width using multiphase clock signals generated from a ring oscillator. These clocks, which have the same frequency and are evenly spaced, give multiple rising edges within a clock cycle. Thus, it is possible to measure a pulse width more accurately than with existing single clock-based methods. The proposed method is applied to a capacitive touch switch. Experimental results show that the capacitive touch switch with the proposed method gives a 118 fF resolution, which is 6.4 times higher than that of the touch switch with a single clock-based pulse width measurement method.