• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.405-414
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• 2016

IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.12
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• pp.1644-1651
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• 1995

A data and clock recovery integrated circuit for MAC (Multiplexed Analog Component) TV standard is described. The chip performs the recovery of a system clock from a digitally encoded voice signal, clamping of a video signal for DC-level restoration, and precise gain control of a video signal in the presence of a large amplitude variation. A PLL (Phase Locked Loop) is used for timing recovery and a new gain control circuit is proposed which enhances its accuracy and dynamic range by employing two identical four-quadrant analog multipliers. The chip is designed in full custom with 1.5um BiCMOS technology, and layout verification is completed by post-simulation with the extracted circuit.

• The KIPS Transactions:PartA
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• v.19A no.4
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• pp.181-186
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• 2012

The distributed measurement and control system require technology to solve complex synchronization problem among distributed devices. It can be solved by using IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems to synchronize real-time clocks incorporated within each component of the system. In this paper, we implemented the IEEE 1588v2 PTP emulator on BlueScope BL6000A using a delay request-response mechanism to measure clock synchronization.

• Journal of Korea Multimedia Society
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• v.8 no.10
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• pp.1403-1410
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• 2005

The synchronization problem is directly related to the quality of service in multimedia communication and especially in real-time communication. In this study, we found the cause of clock fluctuation between encoder and decoder in MPEG-2 system layer was that the standard decoder design only considered a fixed time delay component. To solve it, we proposed Extended-SRTS algorithm, which uses STC as service clock by synchronizing transport stream. As the result, we can improve the effect of frequency-drift, time-varying-network-jitter and packing-jitter and so on And by virtue of this algorithm, we can make low the dependency of network clock, which makes easy to synchronize and connect transparently at the ends point, we expect the proposed algorithm can be widely applied to the field of real -time multimedia communications.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.5
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• pp.1-8
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• 2005

SPEC CPU2000 is an widely used benchmark program, both in industry and in academy, for measuring compute-intensive performance of computer systems with various architectures. However, there has been little effort to investigate its characteristics with respect to hardware components. This paper presents the performance scalability of SPEC CPU2000 benchmark over CPU clock speed. For an Intel x86-based system running at various clock speed, we measure the performance of SPEC CPU2000 benchmark, and analyze the characteristic of SPEC CPU2000 in a system aspect. In the experiment, we found that the overall performance of SPEC CPU2000 increases monotonically and linearly as the CPU clock speed increases and that the scale efficiencies of SPEC CPU2000 component benchmarks are quite evenly distributed.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.500-503
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• 2008

분산 컴포넌트 시스템에서 여러 컴포넌트가 맞물려 서비스를 수행할 때 기준이 되는 시간이 필요하고 각 컴포넌트 별로 시간 오차가 발생하는 상황에서 시간 동기화 과정이 필요하다. 안정성이 중요시되고 실시간성을 보장하고자 하는 시스템에서 동기화된 시간의 정밀도는 중요한 이슈가 되고 있는데 현재까지 제안된 시간 동기화를 그대로 사용할 경우 발생할 수 있는 딜레이 요소들로 인해 동기화된 시간의 정밀도가 떨어진다. 따라서 본 논문에서는 실제 환경에 시간 동기화가 이루어질 때 오차를 발생시키는 요소들을 지적하고 보완할 수 있는 방법들은 제안함으로써 시간 동기화의 정확도를 높인다.

• Journal of the Korea Institute of Military Science and Technology
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• v.11 no.6
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• pp.148-155
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• 2008

We investigated the damage effects of microcontroller devices under high power electromagnetic(HPEM) wave. HPEM wave was radiated from the open-ended standard rectangular waveguide(WR-340) to free space. The influence of different reset-, clock-, data-, and power supply-line lengths has been tested. The susceptibility of the tested microcontroller devices was in general much influenced by clock-, reset-, and power supply-line length, little influenced by data-line length. Further the line length was increased, the malfunction threshold was decreased as expected, because more energy couples to the devices. The surfaces of the destroyed microcontroller devices were removed and the chip conditions were investigated with microscope. The microscopic analysis of the damaged devices showed component and bondwire destructions such as breakthroughs and melting due to thermal effects.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.959-962
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• 2003

At the processing capabilities and operating frequency of embedded system are growing, so is the needed data bandwidth to fully utilize the processing capability. The ability to transfer huge amount of data between the embedded core and external devices is required for efficient system operation. In this paper, the data communication architecture for the mixed-clock system is proposed. The dynamic priority adaptation algorithm for bus arbitration is proposed for bandwidth guarantee. The communication architecture that incorporates the proposed arbitration algorithm adapts the priority of communication components dynamically based on the information from FIFO. The experiments show that the measured bandwidth of each component traces the required bandwidth well compared to the other arbitration algorithms

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1102-1106
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• 2004

Main component of phase time error of clocks in communication systems is flicker noise. This paper describes computer simulation algorithm of clock error. First, the standard for clock stability is introduced. Flicker noise is generated from white noise sequences by means of an algorithm. Relation between stage number, time constant and bandwidth are introduced. With the help of this algorithm, flicker noise is generated.

• The Journal of the Acoustical Society of Korea
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• v.15 no.2E
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• pp.24-32
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• 1996

A rigorous theory for modeling, analysis, optimum nonseparable filter bank in multidimensional M-band quantized subband codec are developed in this paper. Each pdf-optimized quantizer is modeled by a nonlinear gain-plus-additive uncorrelated noise and embedded into the subband structure. We then decompose the analysis/synthesis filter banks into their polyphase components and shift the down-and up-samplers to the right and left of the analysis/synthesis polyphase matrices respectively. Focusing on the slow clock rate signal between the samplers, we derive the exact expression for the output mean square quantization error by using spatial-invariant analysis. We show that this error can be represented by two uncorrelated components : a distortion component due to the quantizer gain, and a random noise component due to fictitious uncorrelated noise at the uantizer. This mean square error is then minimized subject to perfect reconstruction (PR) constraints and the total bit allocation for the entire filter bank. The algorithm gives filter coefficients and subband bit allocations. Numerical design example for the optimum nonseparable orthonormal filter bank is given with a quincunx subsampling lattice.