• 전자공학회논문지SC
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• 제37권2호
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• pp.77-84
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• 2000

본 논문에서는 51.84Mbps의 전송 속도를 갖고, 16-QAM 변조방식을 사용하는 VDSL(고속 디지털 가입자 루프) 시스템에서, 전송 신호 주파수 스펙트럼의 밴드-에지 성분을 최대화함으로써 심볼 클록(12.96㎒)을 복원하는 방식에 대해 논의한다〔1〕. 디지털 방식의 PLL에서 여러 가지 특성들이 조사되었으며, NCO(Numerically Controlled Oscillator)에서 사용하는 룩-업 테이블의 효율적인 설계 방식을 제시하였다.

• ETRI Journal
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• 제33권3호
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• pp.326-334
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• 2011

This paper outlines the time jitter effect of a sampling clock on a software-defined radio technology-based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high-speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal-to-noise ratio (SNR) characteristics of a digital IF transceiver with an under-sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency-division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.

• 한국인터넷방송통신학회논문지
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• 제15권3호
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• pp.91-98
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• 2015

제한된 스펙트럼 자원의 효율적 사용을 위한 하나의 해법으로 GPS 시각 기반의 이동선형주파수변조(SLFM)를 갖는 동일채널 다중국소 레이더 운용을 위한 방법을 제시한다. 제안된 알고리즘은 선택된 SLFM 신호 중에 상호상관 특성으로부터 허용할 수 있는 최소상관 수준을 갖는 SLFM 후보군을 찾는다. 제안 방법의 검증을 위해 단일 톱니 또는 삼각 LFM 신호를 갖는 동일채널에 운용되는 수 개의 레이더에 대해 수치해석을 하였다. 간섭 및 잡음, 알고리즘 한계, 그리고 SLFM 신호의 시각 동기 오류에 대해 탐지 거리 및 거리 윤곽의 계산 결과를 고찰하였다.

• 전기학회논문지
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• 제57권12호
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• pp.2263-2268
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• 2008

We investigated the malfunction and destruction characteristics of microcontroller devices under high power electromagnetic(HPEM) wave by magnetron. HPEM was rated at a microwave output of 0 to 1,000 W, at a frequency of 2,450${\pm}$50 MHz and was radiated from the open-ended standard rectangular waveguide(WR-340) to free space. The influence of different reset-, clock-, data-, and power supply-line lengths has been tested. The variation of the line length was done with flat cables. The susceptibility of the tested microcontroller devices was in general much influenced by clock-, reset-, and power supply-line length, little influenced by data-line length. Further the line length was increased, the malfunction threshold was decreased as expected, because more energy couples to the devices. The surfaces of the destroyed microcontroller devices were removed and the chip conditions were investigated with microscope. The microscopic analysis of the damaged devices showed component and bondwire destructions such as breakthroughs and melting due to thermal effects. The obtained results are expected to provide fundamental data for interpreting the combined mechanism of microcontroller devices in an intentional microwave environment.

• Journal of Communications and Networks
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• 제6권2호
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• pp.93-105
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• 2004

This paper discusses cyclostationary interference suppression for multiuser wired communication systems. Crosstalk interference from digital signals in multipair cables has been shown to be cyclostationary. Many crosstalk equalization or suppression techniques have been proposed which make implicit use of the cyclostationarity of the crosstalk interferer. In this paper, the convergence and steady-state behaviors of a fractionally spaced equalizer (FSE) in the presence of multiple cyclostationary crosstalk interference are thoroughly analyzed by using the equalizer's eigenstructure. The eigenvalues with multiple cyclostationary interference depend upon the folded signal and interferer power spectra, the cross power spectrum between the signal and the interferer, and tile cross power spectrum between the interferers, which results in significantly different initial convergence and steady-state behaviors as compared to the stationary noise case. The performance of the equalizer varies depending on the relative clock phase of the symbol clocks used by the signal and multiple interferers. Measued characteristics as well as analytical model of NEXT/FEXT channel are used to compute the optimum and worst relative clock phases among the signal and multiple interferers.

• 센서학회지
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• 제24권6호
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• pp.359-363
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• 2015

This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has n-bit resolution, which typically is limited by conversion time taking up to $2^n$ clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudo-pipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.

• 전자공학회논문지A
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• 제28A권11호
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• pp.910-914
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• 1991

This paper describes the improvement of frequency characteristic of crystal oscillator I.C using Ti-Salicide. The characteristics of transistor(drive current) using Ti-Salicide process are better than Poly-Si process, because the mobility. To know frequency characteristic of oscillator I.C, the simulation is performed using inverter buffer chain of Fan-out 10 TTL. Its result shows at once the generation of normal clock pulse in input signal and the improvement of rising and falling time.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.277-280
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• 2002

This paper analyze the characteristics of three multipliers in finite fields GF(2m) from the point of view of processing time and area complexity. First, we analyze structure of three multipliers; 1) LSB-first systolic array, 2) LFSR structure, and 3) CA structure. To make performance analysis, each multiplier was modeled in VHDL and was synthesized for FPGA implementation. The simulation results show that LFSR structure is best from the point of view of area complexity, and LSB systolic array is best from the point of view of processing time per clock.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.487-488
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• 2006

In this paper, we analyzed the FBGA packages operating in high speeds and high frequency rates for DRAM. Using 3D simulations, we could extract s-parameters of packages. We realize that the proposed FBGA package does not operate properly at 3Gbps bacause the FBGA package have delta-I noise($V_{{\Delta}I-peak}$) of 132.0mV and crosstalk of 300mV, which is 25% of the operating clock level.

• Journal of Power Electronics
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• 제10권3호
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• pp.228-234
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• 2010

This paper investigates the conducted-noise characteristics of a digitally-controlled randomly-switched dc-dc converter. In order to investigate the effect of the suggested digital controller on the conducted-noise characteristics of a dc-dc converter, three factors have been studied: the field-programmable gate array (FPGA) clock speed, the randomization ratio percentage, and the effect of using a closed loop feedback controller. A field-programmable gate array is much more flexible than analog control circuits, has a lower cost, and can be used for power supply applications. A novel FPGA-based implementation has been suggested for obtaining the experimental validations and realizing the studied concepts. Furthermore, the experimental results have been discussed and design guidelines have been included.