• Journal of the Korean Institute of Telematics and Electronics
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• v.9 no.4
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• pp.33-37
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• 1972

Amplifier circuits with differential characteristics, that is, amplifier circuits the voltage gain of which are proportional to the complex frequency are described. It is shown that the characteristics of the circuit predicted on the basis of the nullator-norator model of the transistor coincides with the result of the exact analysis of the circuit, and experimental result coincides with the theory.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.1
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• pp.13-23
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• 1983

This paper deals with the three-level PLA constructed by EXCLUSIVE-OR, AND, and OR. (abbreviated as EXANOR). Most PLA circuits have constraints on minimum chip area and minimal input lines. Thus, the reduction of PLA chip area is an important factor in design of logic circuits. In this paper, newly constructed architecture of PLA is proposed and then, its reduction effect is proved theoretically and some of selected examples are illustrated for designing three-level PLA circuits.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1632-1636
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• 2005

This paper presents synchronization of two identical Modified Chua's circuits using two strategies of error feedback coupling. In the first method the synchronization is achieved by linear unidirectional and in the second one by linear bidirectional error feedback coupling. Both proposed methods can make the states of the Modified Chua's circuits globally asymptotically synchronized. Numerical results are provided to show the effectiveness of the proposed approaches and to compare them together based on different criteria.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.674-676
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• 2008

An electrostatic discharge (ESD) or a noise supplied from the outside has an effect on communication between the timing controller (TCON) and the memory element (EEPROM) through the interface between the timing controller and the memory element in liquid crystal displays (LCD). Therefore, we must apply ESD protection methods to LCD operating circuits for a normal operation. Our ESD protection circuit is to prevent from bi-directional communication errors between TCON and EEPROM due to an electrostatic discharge (ESD).

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.24-25
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• 2008

An Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics, especially for RF (Radio Frequency) integrated circuits (ICs). This paper reviews design and analysis of on-chip ESD (electrostatic discharge) protection circuits for RF applications. Key issues in RF ESD protection, design methods, and RF ESD protection solutions are discussed.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.124.4-124
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• 2001

It needs a skillful experience to design and implement sequential circuits with a relay circuit or LD (Ladder Diagram). One makes out the operation of relay contacts sequentially in case of analyzing a relay circuit or LD. Still more, the design and analyzing of a complex relay circuit or LD are difficult. In this paper, we propose the EMFG (Extended Mark Graph) representation on relay circuits and LD.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.149-152
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• 2002

The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.12-19
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• 1997

In this paper, we present a logic synthesis algorithm for low powr design fo combinational circuits. The proposed algorithm reduces power dissipation by eliminating unnecessary signal transitions. The proposed algorithm restructures a given circuit by using a kernel as prediction logic in a precomputation-based scheme such that switching activity of circuit can be minimized. Experimental results show that the system is efficient for low power design of combinational circuits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.106-115
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• 1994

This paper presents the design of a technology mapping system for optimizing delays of combinational and synchronous sequential logic circuits. The proposed system performs delay optimization for combinational logic circuits by remapping, buffering, and gate merging methods through the correct delay calculation in which the loading values are considered. To get time optimized synchronous sequential circuits, heuristic algorithms are proposed. The proposed algorithms reallocate registers by considering the critical path characteristics. Experimental results show that the proposed system produces a more optimized technology mapping for MCNC benchmarks compared with mis-II.

• Journal of the Korean Society of Safety
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• v.15 no.1
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• pp.93-99
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• 2000

This paper presents a study on the assessment of electrical fire hazards by electric circuits with leakage. The hazards are evaluated with the energy supplied by earth-leakage currents which flow in the circuits simulating the actual circuit of domestic premises. Also, operating time and current of ELB are measured by an experimental approach. A common specification of ELB used in this paper has a sensitivity of 30[mA] for leakage current working on the current-balance principle. Total charges and energy of leakage currents are calculated quantitatively by a theoretical approach and compared with the results obtained from experiments.