• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.38-45
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• 2000

In this paper, an approach of modeling the optical interconnection system by SPICE simulation is presented. SPICE simulations with equivalent circuit models for optical devices are performed in a stable manner. From the simulated results, eye diagrams for receiver output and BER are obtained. Timing jitter due to laser diode turn-on delay effects can be found under various bias conditions. Using this approach, various system parameters such as bit rate, BER, dissipated transmitter power, and bias conditions can be optimized. It is expected that this approach will find useful applications such as Gigabit Ethernet and ATM.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• Communications of Mathematical Education
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• v.28 no.3
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• pp.339-352
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• 2014

In this paper we introduce mathematical modellings in teaching and learning differential equations which were adopted by 2009 revised curriculum. The textbook of 'Advanced Mathematics II' published in 2014 with one publisher includes the content of the second order differential equation y"+y=0 by the power series method. This paper discusses the issue of the power series and gives an alternative method to explain problems of differential equation. Also, we found that the textbook of 'Advanced Mathematics II' used the mechanical system not electrical system in solving differential equation problems. Thus this paper suggests a method using an electric circuit in teaching and learning the first order differential equation. Finally we suggest some terminologies in the teaching and learning of differential equations.

• Journal of the Korean Society for Precision Engineering
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• v.26 no.11
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• pp.138-145
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• 2009

A suspended membrane micro fluidic heat flux sensor that is able to measure the heat flow rate was designed and fabricated by a complementary-metal-oxide-semiconductor-compatible process. The combination of a thirty-junction gold and nickel thermoelectric sensor with an ultralow noise preamplifier, low pass filter, and lock-in amp has enabled the resolution of 50 nW power and provides the sensitivity of $11.4\;mV/{\mu}W$. The heater modulation method was used to eliminate low frequency noises from sensor output. It is measured with various heat flux fluid of DI-water to test as micro fluidic application. In order to estimate the heat generation of samples from the output measurement of a micro fluidic heat-flux sensor, a methodology for modeling and simulating electro-thermal behavior in the micro fluidic heat-flux sensor with integrated electronic circuit is presented and validated. The electro-thermal model was constructed by using system dynamics, particularly the bond graph. The electro-thermal system model in which the thermal and the electrical domain are coupled expresses the heat generation of samples converts thermal input to electrical output. The proposed electro-thermal system model shows good agreement with measured output voltage response in transient state and steady-state.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.18 no.6
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• pp.632-641
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• 2008

This paper is concerned with the development of the piezoelectric energy harvesting(PEH) device for ubiquitous sensor node(USN). The USN needs auxiliary power to lengthen its operational life. In this study, the piezoelectric energy harvesting system consisting of a cantilever with a tip mass and piezoelectric wafer was investigated in detail both theoretically and experimentally. The dynamic model for the addressed system was derived using the assumed mode method. The resulting equations of motion were expressed in matrix form, which had never been developed before. The power output characteristics of the PEH was then calculated and discussed. Various experiments were carried out to investigate the charging characteristics of electrical components. Theoretical and experimental results showed that the PEH was able to charge a battery with ambient vibrations but still needed an effective mechanism which can convert mechanical energy to electrical energy and an optimal electric circuit which dissipates small energy.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.2
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• pp.83-91
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• 2012

An RF energy detector for spectrum sensing in TV white space transceiver is presented. It is based on an RF active filtering technique that comprises a low-noise amplifier with a frequency-translation high-pass filtering feedfoward loop, which attenuates the unwanted sideband energy and only passes the wanted band energy. Unlike the conventional architecture, a new architecture that can attenuate both sidebands at the same time is proposed. A simplified system modeling method is presented to assess the non-ideality effects on the RF energy detector performances. System behavioral simulations demonstrate that the proposed architecture can be instrumental for realizaing a RF energy detector circuit in CMOS.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.1
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• pp.129-137
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• 2017

In this paper, we propose a digital controller design methodology for an LLC resonant converter which has been widely used due to the advantages of low switching loss and high efficiency. We establish a mathematical model of an LLC resonant converter using the extended describing function concept and propose a controller design method based on the Ziegler Nichols control parameter tuning criteria. The voltage controller of an LLC resonant converter is designed based on the derived small signal model and the performance of the controller is verified by MATLAB simulations. The validity and the control performance of the designed voltage controller for the LLC resonant converter is analyzed through some simulations for the case of load variations and circuit modeling errors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.101-112
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• 2004

In this paper, we developed a numerical analysis model by using ADI-FDTD method to analyze three-dimensional interconnect structure. We discretized maxwell's curl equation by using ADI-FDTD. Using ADI-FDTD method, a sampler circuit designed from 3.3 V CMOS technology is simplified to 3-metal line structure. Using this simplified structure, the time delay and signal distortion of complex interconnects are investigated. As results of simulation, 5∼10 ps of delay time and 0.1∼0.2 V of signal distortion are measured. As demonstrated in this paper, the full-wave analysis using ADI-FDTD exhibits a promise for accurate modeling of electromagnetic phenomena in high-speed VLSI interconnect.

• ETRI Journal
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• v.20 no.2
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• pp.115-132
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• 1998

This paper proposes an extended service filtering technique to prevent overload in service control point (SCP) due to televoting (VOT) or mass calling (MAS) services with the heavy traffic characteristics. Also, this paper compares this extended technique with the existing overload control techniques, and calculates steady state call blocking probabilities in intelligent network (IN) under overload conditions. The proposed technique considers SCP overload and IN Capability Set (CS)-1 services (such as VOT or MAS service) that have to use the specialized resources of intelligent peripheral (IP). This technique uses first an activating step in which SCP requests service filtering to service switching point (SSP). Then, in the filtering step, SSP sends filtering results to SCP periodically or each N-calls. Also, when filtering time-out expires, SSP stops service filtering, and sends service filtering response to SCP in the deactivating step. This paper applies this technique to VOT/MAS service, and calculates SCP and SSP-IP (circuit) call blocking probabilities by using an analytical VOT/MAS service model. With the modeling and analyzing of this new technique, it shows that this technique reduces the traffic flow into SCP from SSP and IP prominently.