• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.662-665
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• 2002

This paper describes a novel converter to implement high-speed binary-to-residue conversion for moduli 2$^{n}$ - 1, 2$^{n}$ , 2$^{n}$ +2$^{\alpha}$/($\alpha$$\in$｛0,1,…,n-1｝) without using look-up table. In our implementation, the high-speed converter can be achieved, because of the modulo addition time is independent of the word length of operands by using the Signed-Digit (SD) adders inside the modulo adders. For a LSI implementation of residue SD number system with ordinary binary system, the proposed binary-to-residue converter is the efficient circuit.cient circuit.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.131-134
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• 2000

This paper presents the circuit design and implementation of a HomePNA (Home Phoneline Network Alliance) 1M8 PHY transceiver for specification ver1.1. This paper describes a physical medium interface, an Ethernet MAC controller unit interface, and a management interface of the HomePNA transceiver. The designed HomePNA transceiver can support any specifications having more than 32Mbits/sec(maximum in HomePNA ver2.0) transmission rate by changing physical medium interface, because Ethernet MAC controller unit interface has been designed by using MII.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.819-822
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• 1998

A new active power filter (APF) circuit with a current compesation estimation method is proposed. The current compensation estimation method replaces a current sensor with an estimating circuit and therefore reduces the implementation cost In addition, a simple control scheme, based on the energy balance concept, is adopted to control the voltage of a DC capacitor. Therefore energy change in the DC capacitor can be compensanted in the next cycle. Since a sampling technique is used, a larger DC capacitor voltage ripple can be permissible and a relatively smaller DC capacitor can be used. The proposed method has advantages of the reduction of one current sensor, low implementation cost, and fast transient responses. The theoretical analysis and simulation results are given. The proposed control method is successfully verified by computer simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.3
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• pp.553-561
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• 2001

Chua's oscillator is a simple electronic circuit which exhibits a variety of bifurcation phenomena and attractors, It consist of two capacitors, an inductor, two linear resistors, and a nonlinear resistor. When the circuit exhibits chaotic signals, the nonlinear resistor of Chua's oscillator may have six different voltage - current characteristics. In this paper, the design methodology for practical implementation of the nonlinear resistors which have all these characteristics is described. In addition, the effectivness of result is shown by not only the computer simulation but also the experimental test.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.477-483
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• 2015

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.3
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• pp.217-226
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• 1986

A method on the hardware implementation of the Multi-channel FIR digital filter using Digital Quarter Square Multiplication(DQSM) algorithm is proposed. This paper describes that ROM requirement can be reduced by using the double precision algorithm and the absolute value circuit, and also execution speed can be improved by reducing logic level steps of absolute value circuit. The frequency response of the four channel FIR digital filter implemented by the above method is quite agreeable with the frequency response simulated by Remez excahange algorithm.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1284-1287
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• 2002

A fast algorithm for a circular pattern recognition from a binary edge image is proposed in this paper. The implementation of this algorithm onto an FPGA is designed using Verilog-HDL where a target device is Altera EPF10K100ARC240-3. For a 256 ${\times}$ 256-pixe1 binary edge image assuming a real watermelon in a greenhouse, improved circuit performance of the proposed design was confirmed.

• Journal of IKEEE
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• v.22 no.3
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• pp.846-849
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• 2018

Wireless power transfer (WPT) is the technology that enables the power to transmit electromagnetic field to an electrical load without the use of wires. There are two kinds of magnetic resonant coupling and inductive coupling ways transmitting from the source to the output load. Compared with microwave method for energy transfer over a long distance, the magnetic resonance method has the advantages of reducing the barrier of electromagnetic wave and enhancing the efficiency of power transmission. In this paper, the wireless power transfer circuit having a resonant frequency of 13.45 MHz for the low power system is studied, and the hardware implementation is accomplished to measure the power transmission efficiency for the distance between the transmitter and the receiver.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1947-1948
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• 2008

This paper presents the implementation of Power Line Communication(PLC) module which can reduce standby-power consumption. The suggested PLC module consists of PLC modem, coupling circuit, ZCP(Zero-Cross Point) Circuit and main SMPS control relay. The test results under power line communication test-bed used home appliance show the 77% saving of standby-power.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.481-484
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• 2002

In recent, the contactless IC card is widely used in traffic, access control system and so forth. And its use becomes a general tendency more and more because of the development of RF technology and improvement of requirement for user convenience. This paper describes the hardware module to process contactless protocol for implementation contactless IC card. And the hardware module consists of specific digital logic circuits that analyze digital signal from analog circuit and then generate data & status signal for CPU, and that convert the data from CPU into digital signal for analog circuit.