• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.1
• /
• pp.131-143
• /
• 1996

In this paper, we propose the improved structure of fully interconnected ATM Switch to develop the small sized switch element and represent practical implementation of switch network. As the part II of the full study about structure and implementation of fully interconnected ATM Switch, this paper especially describes the implementation of an ATM switching element with 8 input port and 8 output port at 155 Mbits/sec each. The single board switching element is used as a basic switching block in a small sized ATm switch for ATM LAN Hub and customer access node. This switch has dedicated bus in 12 bit width(8 bit data + 4 bit control signal) at each input and output port, bit addressing and cell filtering scheme. In this paper, we propose a practical switch architecture with fully interconnected buses to implement a small-sized switch and to provide multicast function withoutany difficulty. The design of switching element has become feasible using advanced CMOS technology and Embedded Gate Array technology. And, we also represent Application Specific Integrated Circuit(ASIC) of Switch Output Multiplexing Unit(SOMU) and 12 layered Printed Circuit Board for interconnection network of switch.

• ETRI Journal
• /
• v.42 no.4
• /
• pp.534-548
• /
• 2020

This study presents a new architecture for a field programmable analog array (FPAA) for use in low-frequency applications, and a generalized circuit realization method for the implementation of nth-order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA-C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA-C symmetric balanced structure for even/odd-nth-order low-pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90-nm complementary metal-oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low-power designs for implementation of biopotential signal processing systems.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.33B no.3
• /
• pp.186-192
• /
• 1996

A modified learning rule is introduced for the implementation of feedforward artificial neural networks with on-chip learning circuitry using standard analog CMOS technology. Learning rule, is modified form the EBP (error back propagation) rule which is one of the well-known learning rules for the feedforward rtificial neural nets(FANNs). The employed MEBP ( modified EBP) rule is well - suited for the hardware implementation of FANNs with on-chip learning rule. As a ynapse circuit, a four-quadrant vector-product linear multiplier is employed, whose input/output signals are given with voltage units. Two $2{\times}2{\times}1$ FANNs are implemented with the learning circuitry. The implemented FANN circuits have been simulatied with learning test patterns using the PSPICE circuit simulator and their results show correct learning functions.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.6
• /
• pp.1533-1545
• /
• 1996

In this paper, the design and implementation of echo canceller with new variable step size algorithm is discussed. The method used in the new algorithm is to periodically adopt the test function which helps an optimal coefficient tracking. This algorithm outperforms LMS and VS algorithms in convergence speed and steady state error. As the period of test function is decreased, the speed of convergence is improved, but the number of calculation is increased, then the trade off between these parameters must be considered. Simulation results show new algorithm outperforms LMS and VS algorithms in convergence rate. For the design of hardware, circuit is designed with VHDL, and synthesized with Act1 withc is a FPGA library of ActelTM in use of synovation of InterGraph$^{TM}$. Verification of the synthesized circuit is carried out with simulator DLAB. The circuit based on the algorithm which is suggested in this paper calculated 7 radix places of inary number. A simulation data for the verification is based on the data of algorithm simulation. When the same input data is applied to the both simulation, output results of circuit simulation had slight difference in compare with that of algorithm simulation. The number of used gate is about 5,500 and We have 5.53MHz in maximum frequency.y.

• Journal of Advanced Marine Engineering and Technology
• /
• v.21 no.1
• /
• pp.71-81
• /
• 1997

This paper describes an implementation of Chua's oscillator circuits with five - segment piecewise -linear function. Some bifurcation phenomena and chaotic attractors observed experimentally from the laboratory model and simulated by computer for the model are also presented. The Chua's oscillator circuit is implemented with analog electronic devices. Com¬paring both the observations and simulations, the spectrums are satisfactory.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.301-304
• /
• 2002

This paper describes the design and implementation results of JPEG core, based on the ITU-T Recommendation T.81. We designed the RTL circuit in Verilog HDL, making reference to the JPEG program from the Independent JPEG Group. The circuit has been simulated with Verilog-XL, synthesized with Design Compiler and verified using Altera FPGA. Since the synthesized circuit includes a small number of gates, it is expected to be used as a core module in image processing SOC.

• Journal of Advanced Marine Engineering and Technology
• /
• v.22 no.6
• /
• pp.908-919
• /
• 1998

This paper describes implementation and simulation of Chua's oscillator circuits with a cubic non-linear resistor. The two-terminal nonlinear resistor NR consists of one Op Amp two multipliers and five resistors. The Chua's oscillator circuit is implemented with analog electronic devices. Period-1 limit cycle period-2 limit cycle period-4 limit cycle and spiral attractor double-scroll attractor and 2-2 window are observed experimentally from the laboratory model and simulated by computer for the presented model. Comparing the result of experiments and simulations the spectrums are satisfied.

• Proceedings of the Korean Information Science Society Conference
• /
• 2010.06d
• /
• pp.380-383
• /
• 2010

본 논문은 원격에서의 의료 기술이나, 대용량을 요구하는 실시간 협업 등에서 사용자의 요구에 따라 빠르게 요구 대역폭을 할당하고 보장하기 위한 Dynamic Circuit Network 구현 방법을 기술 하였다. 이를 위해 QoS, MPLS, RSVP 기술을 기반으로 2계층의 LSP을 동적으로 할당할 수 있도록 하였으며, 사용자는 이를 웹 기반의 인터페이스(web-based user interface)를 통해 쉽게 서비스 받을 수 있도록 하였다.

• Proceedings of the IEEK Conference
• /
• 2001.06e
• /
• pp.5-8
• /
• 2001

In this paper, we have space vector PWM(Pulse Width Modulation) circuits on the FPGA(Field Programmable Gate Arry) chip designed by VHDL(Very high speed integrated circuit Hardware Description Language). This circuit parts was required at controlling the AC servo motor system and should have been designed with many discrete digital logics. In the result of this study, peripheral circuits are to be simple and the designed logic terms are robust and precise. Because of it's easy verification and implementation, we could deduced that the customize FPGA chip show better performance than that of circuit modules parts constituted of discrete IC.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.59 no.3
• /
• pp.569-574
• /
• 2010

The full bridge converter have been used for high power system that is needed to switch the big current. So, EMI and stability problem is occurred. The Soft switching method is the solution to solve the above problem, But implementation of soft switching(ZVS: Zero Voltage Switching) is so complicate and expensive because of the DSP MCU and shift circuit. In this paper, we introduce the technical method for driving circuit of ZVS full bridge converter with 1st order delay circuit and logic elements. The realization of this method is so simple and cheap. The effectiveness of the proposed circuit is verified by experimental results.