• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.625-626
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• 2006

An Ultra low power super-regenerative oscillator was implemented with on-chip inductor and quench signal generator. The super-regenerative oscillator detects the signal level as low as -70dBm while consuming only 0.48mA at 1.5V supply voltage. These results indicate that the super-regenerative oscillator can be outstanding candidate the simple, ultra low power receiver design.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.207-210
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• 2000

This paper introduces a voltage-mode biquadratic circuit using only Operational Amplifiers (OTAs) and Operational Transconductance Amplifiers (OTAs). The proposed circuit can realize low-pass, band-pass, high-pass, band-stop and all-pass transfer functions by suitably choosing the input and output terminals. And the circuit characteristics can be electronically tuned through adjusting the transconductance gains of OTAs. Some examples are given together with simulated results by PSpice. The circuit configuration is very suitable for implementation in both bipolar and CMOS technologies.

• Proceedings of the KIEE Conference
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• 1995.07b
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• pp.664-666
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• 1995

Chua's circuit is a simple electronic network which exhibits a variety of bifurcation and attractors. The circuit consists of two capacitors, an inductor, a linear resistor and a nonlinear resistor. This paper describes the implementation for a practical op amp of Chua's circuit. In experiment results, 1 periodic motion, 2 periodic motion, rossler type attractors, stranger chaotic attractor periodic window and limit cycle are shown, which are coincide with computer simulation.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.933-936
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• 1993

A high speed fuzzy processor using bipolar technology is proposed in this paper. The hardware system uses a high-speed current-mode membership function circuit and normalization technique. The new membership function circuit generates an ideal membership function of the fuzzy set and its circuit is also simple and available for VLSI implementation. Several techniques have been implemented to speed up response of the processor. The fuzzy processor has been designed and implemented in bipolar circuit technology. The experiments and simulations show that the response speed is below 100ms. It can also be expected that the fuzzy processor can be integrated on one chip and its response time is only about the order of nanoseconds.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.65-70
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• 2001

This paper presents a Receiver MMIC for the CDMA terminal. The complete circuit is composed of Low Noise Amplifier, Down Conversion Mixer, Intermediate Frequency Amplifier and Bias circuit. The Bias circuit implementation, which allows for compensation for threshold voltage and power supply voltage variation are provided. The proposed topology has high linearity and low noise characteristics. Results of the designed circuit are as follows: Overall conversion gain is 28.5 dB, input IP3 of LNA is 8 dBm, input IP3 of down conversion mixer is 0 dBm and total DC current consumption is 22.1 mA.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.111-112
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• 2012

전력효율을 높일 수 있는 DC 전송이 주요 관심사가 됨에 따라 전력품질에 대한 기술이 요구된다. DC 그리드의 전력품질을 위해서는 반도체 차단기(Solid-State Circuit Breaker : SSCB)는 필수요소이다. 하지만 기존의 반도체 차단기는 AC 그리드에 기반을 두고 제안되었기 때문에 DC 그리드에 적용하기 어렵다. 따라서 본 연구에서는 DC 그리드에 적용 가능한 SSCB (Solid-State Circuit Breaker : SSCB)을 제안한다. 제안하는 DC SSCB는 사고 전류를 제한하며 사고 지점의 신속한 차단이 가능하다. 제안한 회로는 시뮬레이션을 통해 단락 사고를 모의하여 시스템의 동작 특성을 검증하였다.

• Proceedings of the KIEE Conference
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• 1983.07a
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• pp.90-92
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• 1983

• Proceedings of the IEEK Conference
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• 2000.06d
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• pp.147-150
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• 2000

Hausdorff distance(HD) commonly used measures for object matching, and calculates the distance between two point set of pixels in two-dimentional binary images without establishing correspondence. And it is realized as the image filter applying the fuzzy. In this paper, the fuzzy hardware realizes in order to construct the image filter applying HD, also, propose as the method for the noise removal using it in the image. MIN-MAX circuit designs the circuit using MAX-PLUS, and the fuzzy HD hardware results are obtained to the simulation. And then, the previous computer simulation is confirmed to the result by using MATLAB.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.950-953
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• 1987

A wave difference method(WDH) phase detector for timing recovery is designed in the digital subscriber loop receiver. This paper describes the architecture and experimental results of the WDM, tankless timing extraction PLL. The results show that the designed WDM timing extraction circuit have stable jitter performance without the use of high precision LC tank circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.141-145
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• 1998

This paper CMOS full adder design method based on carry-propagation-free addition trees and a circuit technique, so called multiple-valued current-mode (MVCM) circuits. The carry-paopagation-free addition method uses a redundant digit sets called redundant positive-digit number representations. The carry-propagation-free addition is by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuit. We demonstrate the effectiveness of the proposed method through simulation(SPICE).