• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.529-532
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• 1988

This paper proposes a graph matching algorithm based on simulated annealing, which assures the globally optimal solution for circuit partitioning for the placement in the rectilinear region occurring as a result of the pre-placement of some macro cells, or onto the nonplanar surface in some military or space applications. The circuit graph ($G_{C}$) denoting the circuit topology is formed by a hierarchical bottom-up clustering of cells, while another graph called region graph ($G_{R}$) represents the geometry of a planar rectilinear region or a nonplanar surface for circuit placement. Finding the optimal many-to-one vertex mapping function from $G_{C}$ to $G_{R}$, such that the total mismatch cost between two graphs is minimal, is a combinatorial optimization problem which was solved in this work for various examples using simulated annealing.

• 정보처리학회논문지A
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• 제9A권1호
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• pp.61-74
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• 2002

본 논문에서는 시간 제한 조건을 가진 자유 선택 신호 전이 그래프로부터 비동기 회로를 합성하는 방법을 기술한다. 이 방법에서는 상태 그래프를 생성하지 않고 신호 전이 그래프로부터 직접 신호 전이들간의 관계를 구하여 비동기 회로를 합성한다. 본 논문의 합성 방법에서는 자유 선택 신호 전이 그래프를 선택 행위가 없는 결정성 신호 전이 그래프에 대하여 타이밍 분석을 수행하여 임의의 두 신호 전이 사이의 시간 제약 병렬 관계와 시간 제약 인과 관계를 구한다. 다음에는 이 관계들을 이용하여 각 결정성 신호 전이 그래프에 대한 합성을 수행하고 그 결과를 합병함으로써 전체 회로를 합성한다. 실험 결과에 의하면 본 논문에서 제안한 합성 방법은 상태 공간이 큰 회로에 대하여 현저하게 합성시간을 단축시킬 수 있을 뿐 만 아니라 기존의 상태 그래프 기반 합성 방법과 비교하여 거의 같은 면적의 회로를 합성한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.883-886
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• 1998

We introduce a high level synthesis methodlogoy for automatic synthesis of asynchronous circuits form a language based on CSP. The input language is a high level concurrent algorithmic specification that can model complex concurrent control flow, logical and arithmetic computation and communications between them. This specification is translated into petri net which has actions. These actions are refined to synthesize the controllers and to allocate the data resources. We use the automatic synthesis through signal transition graphs (STGs) that allows to take advantage of logic synthsis methods to optimize the circuit.

• 대한전자공학회논문지
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• 제24권4호
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• pp.708-712
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• 1987

This paper deals with minimizing layout area of VLSI design. A long wire in a VLSI layout causes delay which can be reduced by using a driver. There can be significant area increase when many drivers are introduced in a layout. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area optimal embeddings for VLSI graphs in rectangles of several aspect ratios.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.825-828
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• 2005

In this paper, we propose a new nonvolatile unit memory cell and proposal peripheral circuit using the polymer material. Memory that relies on bistable behavior- having tow states associated with different resistances at the same applied voltage - has attracted much interest because of its nonvolatile properties. Such memory may also have other merits, including simplicity of structure and manufacturing, and the small size of memory cells. We have plotted the load line graphs for the use of a polymer memory character, hence we have designed in the band-gap reference shape of a write/erase drive, and then designed in the 2-stage differential amplifier shape of a sense amplifier in the consideration of a low current characteristic of a polymer memory cell. The simulation result shows that is has high gain about 80dB by sensing the very small current.

• ETRI Journal
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• 제27권2호
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• pp.195-205
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• 2005

In this paper, an error-free Butcher algorithm is introduced to study the singular system of a linear electrical circuit for time invariant and time varying cases. The discrete solutions obtained using Runge-Kutta (RK)-Butcher algorithms are compared with the exact solutions of the electrical circuit problem and are found to be very accurate. Stability regions for the single term Walsh series (STWS) method and the RK-Butcher algorithm are presented. Error graphs for inductor currents and capacitor voltages are presented in a graphical form to show the efficiency of the RK-Butcher algorithm. This RK-Butcher algorithm can be easily implemented in a digital computer for any singular system of electrical circuits.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 춘계학술대회
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• pp.43-46
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• 2011

A novel circuit structure of dual-band bandstop filters is proposed in this paper. This structure comprises two shunt-connected tri-section stepped impedance resonators with a transmission line in between. Theoretical analysis from the equivalent circuit and design procedures are described. We represented graphs for filter design from the derived synthesis equations by resonance condition of circuits. Notably, advantages of the proposed filter structure are compact size in design, wide range of realizable resonance frequency ratio, and more realizable impedances.

• Smart Structures and Systems
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• 제17권2호
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• pp.327-345
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• 2016

The existence of SH-wave in a piezomagnetic layer overlying an initially stressed orthotropic half-space is investigated. The coupled of differential equations are solved for piezomagnetic layer overlying an orthotropic elastic half-space. The general dispersion equation has been derived for both magnetically open circuit and magnetically closed circuits under the four types of boundary conditions. In the absence of the piezomagnetic properties, initial stress and orthotropic properties of the medium, the dispersion equations reduce to classical Love equation. The SH-wave velocity has been calculated numerically for both magnetically open circuit and closed circuits. The effect of initial stress and magnetic permeability are illustrated by graphs in both the cases. The velocity of SH-wave decreases with the increment of wave number.

• 제어로봇시스템학회논문지
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• 제9권11호
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• pp.952-957
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• 2003

We propose how to translate relay circuits to the EMFGs(Extended Mark Flow Graphs) formally and analyze the original one by using the mark flow of it. Firstly, the concepts of the output condition, the output-on condition and the output-off condition are introduced in the relay circuits. These can be used to find the structure and the operation of respective relay outputs but the sequential operations of them cannot be obtained from these. Secondly, a relay circuit is translated to the corresponding EMFG as the all output-on conditions and all output-off conditions of it are translated to EMFGs. For the adequate translation, the condition arc and the concepts of the generation transition and the degeneration transition are introduced, and the duality for the simplification of the result. Thirdly, we analyze the operation of the original circuit by analyzing the mark flow of the resulting EMFG. We can achieve easy and fast analysis based on the EMFG's operation algorithm. Finally, we apply these to the relay circuit for an electric furnace and analyze its operation with the mark flow of the resulting EMFG. The formal translation from relay circuits to EMFGs makes the analysis easy so that these results can be used to design, modelling, the fault detection and the maintenance.

• 한국정보통신학회논문지
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• 제15권8호
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• pp.1653-1658
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• 2011

본 논문에서는 듀얼 밴드 대역저지 필터의 소형화 설계를 위한 새로운 구조를 제안한다. 본 구조는 전송 라인과 두 개의 병렬로 연결된 3단 계단형 임피던스 공진기로 구성되어 있다. 필터의 등가회로를 통한 이론적 분석과 설계 절차를 나타내었다. 공진조건으로부터 유도한 방정식으로부터 각 설계 변수에 대한 특성 결과를 그래프로 나타내어 설계의 편의성을 제공한다. 제안된 필터 구조의 장점은 설계의 소형화 가능성, 구현 가능한 공진 주파수의 비율이 넓은 점, 그리고 구현 가능한 임피던스의 선택이 자유롭다는 점이다.