• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 1999년도 추계종합학술대회
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• pp.278-281
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• 1999

본 논문에서는 많은 함수를 용이하게 해석하고 테스트할 수 있는 결정도(Decision diagram)에 의한 다치순차논리회로(Multiple valued squential circuit)를 구현하였다 우선, 다치순차 회로의 기억소사는 D F/F를 이용하였으며 전류모드에 의한 결정도 순차 논리 회로를 구현한다 이 회로의 동자특성은 PSPICE 시뮬레이션을 통하여 확인하였다. 본 논문에서 제시한 전류모드 CMOS의 결정도 다치순차회로는 회선 경로 선택의 규칙성, 간단성, 여러함수를 쉽게 해석하고 테스트 할 수 있는 등등의 이점을 가지므로 VLSI화 실현에 적합할 것으로 생각된다.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권5호
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• pp.278-286
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• 2000

A new large-scale network geometric analysis is introduced. For a large-scale circuit, it must be analyzed with a geometric diagram and figure. So many equations are induced from a geometric loop-node diagram. The results are arranged into a simple matrix, of course. In case of constructing a network diagram, it is not easy to handle voltage and current sources together. Geometric loop analysis is related to voltage sources, and node analysis is to current sources. The reciprocal transfer is possible only to have series or parallel impedance. If not having this impedance, in order to obtain equivalent circuit, many equations must be derived. In this paper a loop-reduction method is proposed. With this method current source branch is included into the other branch, and disappears in circuit diagram. So the number of independent circuit equations are reduced as much as that of current sources. The number is not (b-n+1), but (b-n+1-p). Where p is the number of current sources. The reduction procedure is verified with a geometric principle and circuit theory. A resultant matrix can be constructed directly from this diagram structure, not deriving circuit equations. We will obtain the last results with the help of a computer.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.124.4-124
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• 2001

It needs a skillful experience to design and implement sequential circuits with a relay circuit or LD (Ladder Diagram). One makes out the operation of relay contacts sequentially in case of analyzing a relay circuit or LD. Still more, the design and analyzing of a complex relay circuit or LD are difficult. In this paper, we propose the EMFG (Extended Mark Graph) representation on relay circuits and LD.

• Journal of Multimedia Information System
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• 제6권4호
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• pp.323-328
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• 2019

In this paper, a method of constructing an advanced sequential circuit over finite fields is proposed. The method proposed an algorithm for assigning all elements of finite fields to digital code from the properties of finite fields, discussed the operating characteristics of T-gate used to construct sequential digital system of finite fields, and based on this, formed sequential circuit without trajectory. For this purpose, the state transition diagram was allocated to the state dependency code and a whole table was drawn showing the relationship between the status function and the current state and the previous state. The following status functions were derived from the status function and the preceding table, and the T-gate and the device were used to construct the sequential circuit. It was confirmed that the proposed method was able to organize sequential digital systems effectively and systematically.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.108.6-108
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• 2001

The basic circuit block diagram of CMOS current mode sum and subtract circuit is present in this paper. The purpose circuit consists of the invert current circuit and the basic current mirror. The outputs of the circuit are the summing of the both input current [lx+ly] and also the subtract of the both input current [lx+(-ly)]. The SPICE simulation results of the electrical characteristics with level 7 (BSIM3 model version 3.1) MOSFET transistor model of the circuit such as the input dynamic range, the frequency response and some system application have been shown and analyzed.

• Journal of Electrical Engineering and Technology
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• 제10권3호
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• pp.766-776
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• 2015

It is well known that series arc faults in Low Voltage DC (LVDC) distribution system occur at unintended points of discontinuity within an electrical circuit. These faults can make circuit breakers not respond timely due to low fault current. It, therefore, is needed to detect the series fault for protecting circuits from electrical fires. This paper proposes a novel scheme to detect the series arc fault using Wavelet Singular Value Decomposition (WSVD) and state diagram. In this paper, the fault detector developed is designed by using three criterion factors based on the RMS value of Singular value of Approximation (SA), Sum of the absolute value of Detail (SD), and state diagram. LVDC distribution system including AC/DC and DC/DC converter is modeled to verify the proposed scheme using ElectroMagnetic Transient Program (EMTP) software. EMTP/MODELS is also utilized to implement the series arc model and WSVD. Simulation results according to various conditions clearly show the effectiveness of the proposed scheme.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제52권6호
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• pp.262-270
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• 2003

In this paper, the characteristics of single-phase line-start permanent magnet synchronous motor driven by constant voltage are analyzed on d-q axis vector diagram and compared with that of current controlled motor. The coupled method of symmetrical coordinates and d-q axis voltage equation are applied to the analysis method like the analysis of single-phase induction motor. From the result of the analysis, it is seen that motors driven by constant voltage source have effects on not only the amplitude of current and torque but also current and current phase angle, so overall characteristics such as power factor and load angle are affected by circuit parameters. For precise analysis and design of single-phase line-start synchronous motor, its characteristics should be analyzed on d-q axis vector plan in consideration of the variation of circuit parameters.

• 한국정보통신학회논문지
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• 제10권2호
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• pp.228-234
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• 2006

본 논문은 주어진 재귀 DSP 알고리듬으로부터 최적멀티프로세서 스케줄러를 이용하여 완전한 회로도를 효과적으로 생성할 수 있는 체계적인 과정에 대하여 기술한다. 이과정은 크게 스케줄 생성 단계와 회로도 생성 단계로 구성된다. 스케줄 생성 단계는 입력으로서 Fully Specified Flow Graph(FSFG)로 표현된 재귀 DSP 알고리듬을 받아서 최적 멀티프로세서 스케줄러를 생성하며 회로도 생성 단계에서는 이 스케줄러로부터 제어신호를 포함한 완전한 회로도를 생성한다. 이 회로도는 실리콘 컴파일러를 이용하여 VLSI 레이아웃으로 용이하게 변환될 수 있다. 본 논문에서는 2차 Gray-Market Lattice 필터를 예로 사용하여 전체적인 구현과정을 보인다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.69-72
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• 2003

This paper presents a current-mode multiple-input minimum circuit. The proposed circuit can be implemented by applying De Morgan’s law. The circuit diagram is simple and modular. It operates using a single 2.5V supply and has very low dissipation. The realization method is suitable for fabrication using CMOS technology and all transistors are operated in their saturation region. The performances of this proposed circuit were studied using the PSPICE analog simulation program. The simulation results show the approval of this circuit that it has adequate basic performances for a real-time fuzzy controller and a fuzzy computer.

• 전자공학회논문지C
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• 제36C권5호
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• pp.1-12
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• 1999

본 논문에서는 스위치-레벨 회로의 검증(verification)을 위해서 이진 결정 다이어그램(BDD : Binary Decision Diagram)을 구현하는 새로운 알고리즘을 제안한다. 스위치-레벨에서 기능(function)들은 스위치들의 직$\cdot$병렬 연결에 의해서 결정되며, 결과 논리 값은 논리 '0'과 '1'뿐만 아니라, 초기 상태, 고 임피던스와 불안정 상태를 가진다. 따라서, 본 논문에서는 "스위치-레벨 이진 결정 다이어그램(SLBDD : Switch- Level Bianary Decision Diagram)"으로 정의한 비 사이클 그래프(acyclic graph)들을 사용해서 스위치-레벨 회로의 가능들을 표현하도록 BDD를 확장하였다. 그러나, 그래프의 기능적 표현을 최악의 경우 입력 변수들의 수에 지수 함수적이 되므로, 결정 다이어그램의 변수 순서(ordering)는 그래프 크기에 주된 역할을 하게된다. 따라서, 패스-트랜지스터와 도미노-논리가 존재하는 사전에 충전하는 회로(Precharging circuitry)에서 그래프 크기에서의 효율성을 위한 입력 순서 알고리즘을 제안한다. 그리고, 실험 결과는 여러 가지 벤치-마크 회로에서 여러 번의 실험을 통해서 제안된 알고리즘이 스위치-레벨에서의 기능적 시뮬레이션, 전력 측정과 결점 시뮬레이션에 적용될 수 있을 만큼 충분히 효율적임을 보여준다.율적임을 보여준다.