• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.2
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• pp.16-23
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• 2006

This paper presents a novel single-stage high frequency resonant inverter link type DC-DC converter using zero voltage switching with high power-factor. The proposed topology is integrated half-bridge boost rectifier as power factor corrector(PFC) and half-bridge high frequency resonant converter into a single-stage. The input stage of the half-bridge boost rectifier works in discontinuous conduction mode(DCM) with constant duty cycle and variable switching frequency. So that a boost converter makes the line current follow naturally the sinusoidal line voltage waveform. Simulation results have demonstrated the feasibility of the proposed high frequency resonant converter. Characteristics values based on characteristics analysis through circuit analysis is given as basis data in design procedure. Also, experimental results are presented to verify theoretical discussion. This proposed inverter will be able to be practically used as a power supply in various fields as induction heating applications, fluorescent lamp and DC-DC converter etc.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2747-2753
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• 2011

In this paper, a PWM current-mode DC-DC boost converter for mobile phone flash application has been proposed. The converter which is operated with 5 Mhz high switching frequency is capable of reducing mounting area of passive devices such as inductor and capacitor, consequently is suitable for compact mobile phones. This boost converter consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. Meanwhile, the control block consists of pulse width modulator, error amplifier, oscillator etc. Proposed boost converter has been designed and verified in a $0.5\;{\mu}m$ 1-poly 2-metal CMOS process technology. Simulation results show that the output voltage is 4.26 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 Khz driven converter when the duty ratio is 0.15.

• Journal of Satellite, Information and Communications
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• v.2 no.2
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• pp.64-68
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• 2007

This paper describes the development of RF front.end equipment of a wide band high precision satellite navigation receiver to be able to receive the currently available GPS navigation signal and the GALILEO navigation signal to be developed in Europe in the near future. The wide band satellite navigation receiver with high precision performance is composed of L - band antenna, RF/IF converters for multi - band navigation signals, and high performance baseband processor. The L - band satellite navigation antenna is able to be received the signals in the range from 1.1 GHz to 1.6 GHz and from the navigation satellite positioned near the horizon. The navigation signal of GALILEO navigation satellite consists of L1, E5, and E6 band with signal bandwidth more than 20 MHz which is wider than GPS signal. Due to the wide band navigation signal, the IF frequency and signal processing speed should be increased. The RF/IF converter has been designed with the single stage downconversion structure, and the IF frequency of 140 MHz has been derived from considering the maximum signal bandwidth and the sampling frequency of 112 MHz to be used in ADC circuit. The final output of RF/IF converter is a digital IF signal which is generated from signal processing of the AD converter from the IF signal. The developed RF front - end has the C/N0 performance over 40dB - Hz for the - 130dBm input signal power and includes the automatic gain control circuits to provide the dynamic range over 40dB.

• Korean Journal of Remote Sensing
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• v.30 no.2
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• pp.293-302
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• 2014

Radar systems are used in remote sensing mainly as space-borne, airborne and ground-based Synthetic Aperture Radar (SAR), scatterometer and Doppler radar. Those systems are composed of expensive equipments and require expertise and professional skills for operation. Because of the limitation in getting experiences of the radar and SAR systems and its operations in ordinary universities and institutions, it is difficult to learn and exercise essential principles of radar hardware which are essential to understand and develop new application fields. To overcome those difficulties, in this paper, we present the construction and experiment of a low-cost educational radar system based on the blueprints of the MIT Cantenna system. The radar system was operated in three modes. Firstly, the velocity of moving cars was measured in Doppler radar mode. Secondly, the range of two moving targets were measured in radar mode with range resolution. Lastly, 2D images were constructed in GB-SAR mode to enhance the azimuth resolution. Additionally, we simulated the SAR raw data to compare Deramp-FFT and ${\omega}-k$ algorithms and to analyze the effect of antenna positional error for SAR focusing. We expect the system can be further developed into a light-weight SAR system onboard a unmanned aerial vehicle by improving the system with higher sampling frequency, I/Q acquisition, and more stable circuit design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.1-9
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• 2006

In this paper, a couple of 10Gb/s transimpedance amplifiers are realized in a 0.18um standard CMOS technology for optical communication applications. First, the voltage-mode inverter TIA(I-TIA) exploits inverter input configuration to achieve larger effective gm, thus reducing the input impedance and increasing the bandwidth. I-TIA demonstrates $56dB{\Omega}$ transimpedance gain, 14GHz bandwidth for 0.25pF photodiode capacitance, and -16.5dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. However, both its inherent parasitic capacitance and the package parasitics deteriorate the bandwidth significantly, thus mandating very judicious circuit design. Meanwhile, the current-mode RGC TIA incorporates the regulated cascade input configuration, and thus isolates the large input parasitic capacitance from the bandwidth determination more effectively than the voltage-mode TIA. Also, the parasitic components give much less impact on its bandwidth. RGC TIA provides $60dB{\Omega}$ transimpedance gain, 10GHz bandwidth for 0.25pF photodiode capacitance, and -15.7dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. Main drawback is the power dissipation which is 4.5 times larger than the I-TIA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.1
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• pp.114-124
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• 2011

In this paper, we present a 2 GHz compact analog phase shifter with linear phase-tune characteristic. The compact phase shifter was designed base on a lumped all pass network and implemented using a ceramic substrate fabricated with thin-film technique. For a linear phase-tune characteristic, a capacitance of the varactor diode for a tuning voltage was linearized by connecting series capacitor and subsequently produced an almost linear capacitance change. The inductor and bias circuit in the all pass network was implemented using a spiral inductors for small size, which results in the size reduction to $4\;mm{\times}4\;mm$. In order to measure the phase shifter using the probe station, two CPW pads are included at the input and output. The fabricated phase shifter showed an insertion loss of about 4.2~4.7 dB at 2 GHz band and a total $79^{\circ}$ phase change for DC control voltage from 0 to 5 V, and showed linear phase-tune characteristic as expected in the design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2237-2246
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• 2012

A bias circuit required for an oral sensor is manufactured inside the oral sensor chip to reduce its size and cost. The proposed DC-DC converter supplies the required reference and bias currents for their corresponding regulators by using IREF of the reference current generator. Their target voltages of the voltage regulators are regulated by the negative mechanism by generating their reference voltages required for their corresponding regulators. In addition, a constant current IB0/IB1 is supplied by being mirrored by a current mirror ratio and then VREF is generated. It is confirmed by measurements that the average volatge, ${\sigma}$, and $4{\sigma}$ of the designed DC-DC converter for intra oral sensors with a $0.18{\mu}m$ X-ray CMOS process are within their required ranges. And the line-pair pattern image shows a high-resolution characteristic without blurring. Also, a good oral image can be obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.1-9
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• 2009

In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with $0.13{\mu}m$ thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ${\pm}3LSB$ and ${\pm}1LSB$, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.673-684
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.