• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.89-94
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• 2009

This paper proposes the algorithms that design the highly digital logic circuit and assign the code to each node of DCG(Directed Cyclic Graph) of length ${\zeta}$. The conventional algorithm have some problems, so this paper introduce the matrix equation from DCG of length ${\zeta}$ and proposes highly digital logic circuit design algorithms according to the DCG of length ${\zeta}$. Using the proposed circuit design algorithms in this paper, it become realized that was able to design from former algorithm. Also, making a comparison between the circuit using former algorithm and this paper's, we testify that proposed paper's algorithm is able to realize more optimized circuit design. According to proposed circuit design algorithm in this paper, it is possible to design current that DCG have natural number, so it have the following advantages, reduction of the circuit input/output digits, simplification of circuit composition, reduction of computation time and cost. And we show comparability and verification about this paper's algorithm.

• Journal of Power Electronics
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• v.19 no.2
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• pp.394-402
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• 2019

This paper proposes a single-phase non-isolated onboard battery charger (OBC) for electric vehicles (EVs) that only uses small film capacitors at the DC-link of the AC-DC converter. In the proposed charger, an isolated DC-DC converter for low-voltage batteries is used as an active power decoupling (APD) circuit to absorb the ripple power when a high-voltage (HV) battery is charged. As a result, the DC-link capacitance in the AC-DC converter of the HV charging circuit can be significantly reduced without requiring any additional devices. In addition, some of the components of the proposed circuit are shared in common for the different operating modes among the AC-DC converter, LV charging circuit and active power filter. Therefore, the cost and volume of the onboard battery charger can be reduced. The effectiveness of the proposed topology has been verified by the simulation and experimental results.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.819-822
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• 1998

A new active power filter (APF) circuit with a current compesation estimation method is proposed. The current compensation estimation method replaces a current sensor with an estimating circuit and therefore reduces the implementation cost In addition, a simple control scheme, based on the energy balance concept, is adopted to control the voltage of a DC capacitor. Therefore energy change in the DC capacitor can be compensanted in the next cycle. Since a sampling technique is used, a larger DC capacitor voltage ripple can be permissible and a relatively smaller DC capacitor can be used. The proposed method has advantages of the reduction of one current sensor, low implementation cost, and fast transient responses. The theoretical analysis and simulation results are given. The proposed control method is successfully verified by computer simulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.11
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• pp.1233-1240
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• 2014

For the last three decades after the advent of the Toffoli gate in 1980, while many reversible circuit syntheses have been presented reversible embedding methods onto suitable reversible functions, only a few proposed direct irreversible-to-reversible mapping methods without reversible embedding. In this paper we present two effective policies to reduce the gate cost and complexity for the existing direct reversible mapping methods without reversible embedding. In order to develop new cost reduction policies we consider the cost influence of Toffoli module according to NOT gate arrangement in classical circuits. From this we deduced an inverse proportional property between inverting input numbers of classical AND/OR gates and reversible Toffoli module cost based on a fact - the inverting inputs of classical AND(OR) gates increase(decrease) the Toffoli module cost. We confirm the applications of the inverting input rearrangement and maximum fan-out policies preceding direct reversible mapping will be effective method to improve the reversible Toffoli module cost and complexity with the parallel using of the fan-out and supercell ones.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.8
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• pp.121-128
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• 2007

In this thesis, we would show how to lay out and produce the shell-type transformer using the world's first Zig-Zag winding way, instead of a general winding. Also, we omit the progress of varnish-impregnation, so that we could develop the new shell-type transformer winding which improves the short-circuit characteristics and dielectric strength. It has a copernican effect to reduce the thickness and the number of insulation papers, as compared with a general winding transformer. We would prove that it is far superior in cost reduction, loss reduction, and mechanical force of short-circuit. And eventually you must find it useful in the pole transformer for power distribution in the domestic power companies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.1
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• pp.92-100
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• 2016

It is informed that the Voice over LTE(VoLTE) which serves voice and message on IP networks is better in terms of economies of scale than the legacy voice service on 2G/3G circuit-switched networks because of its technological and cost efficiency. In addition, services of voice and data are running on a single LTE network and as a result VoLTE has the more economies of scope. But, there is no study about how much technology-efficiency VoLTE has compared to circuit-based voice service and how much voice charge can be reduced as VoLTE grows up. This paper analyzes empirically cost-efficiency of VoLTE against circuit-based voice service and quantifies the reduction of voice charge as 2G/3G voice traffic shifts to VoLTE. The results describe the first is that the average cost of the total voice traffic rises shortly just after the investment of LTE network for providing VoLTE but it will soon have a capacity available to reduce the charge due to VoLTE's outstanding cost efficiency on the assumption that voice traffic is fixed, and the second is that the charge can be cut to 60% of the current rate in case of all the voice traffic moves to VoLTE. The latter proves partially the validation of data-focusing pricing plan. Our results are expected to become basic data for network operators' establishing pricing strategies and for policy makers' inducing price cutting.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.839-841
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• 2004

This paper presents a SPMSM servo motor drive system using high performance TMS320 F281T DSP for the industrial application. This high performance DSP contains some special peripheral circuits such as PWM (Pulse Width Modulation) waveform generation circuit, Quadrature Encoder Pulse (QEP) generation circuit and Analog to Digital Converter (ADC) circuit. In this paper, a servo drive control system is constructed using high performance DPS for the overall system cost reduction and the size minimization.

• Proceedings of the KSME Conference
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• 2000.11a
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• pp.829-836
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• 2000

High performance laser printer requires high speed scanning motor, which can operate up to 40,000 rpm. However, development of high speed scanning motor has been restricted due to the practical problems such as use of high speed bearing, compact circuit design and high cost. In this study, we designed a high speed scanner motor for use on laser scanning unit and discussed some design principles including the reduction method of cogging torque of the motor, development of hemispherical aerodynamic bearing, windage loss estimation, and operating circuit design to reduce noise.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.459-461
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• 2022

One of the big differences between Network-on-Chip (NoC) and the existing parallel processing system based on an off-chip network is that data packet routing is performed using a centralized control scheme. In such an environment, the best-effort packet routing problem becomes a real-time assignment problem in which data packet arriving time and processing time is the cost. In this paper, the Hungarian algorithm, a representative computational complexity reduction algorithm for the linear algebraic equation of the allocation problem, is implemented in the form of a hardware accelerator. As a result of logic synthesis using the TSMC 0.18um standard cell library, the area of the circuit designed through case analysis for the cost distribution is reduced by about 16% and the propagation delay of it is reduced by about 52%, compared to the circuit implementing the original operation sequence of the Hungarian algorithm.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.376-382
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• 2014

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.