• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.171-174
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• 1997

The great development of semiconductor industry demands the high efficiency and performance of related device, but the pick and place system of semiconductor packaging device can load a few units until nowdays. Although the system can load a lot of units, it can work multiple sort operation. The defect like that causes a low efficiency. Therefore, this paper represents the development of pick and place system which can work multiple sort operation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.61-68
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• 2008

This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.568-573
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• 2009

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.

• Korean Journal of Materials Research
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• v.5 no.8
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• pp.929-935
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• 1995

In order to develop COG (Chip On Glass) technology for LCD module interconnecting the driver IC to Al pad electrode on the glass substrate, Anisotropic Conductive Adhesive(ACA) process, the most promising one among COG technologies, was investigated. ACA process was carried out by two steps, dispensing of ACA resin in the bonding area and curing by W radiation. Load on the chip was ranged from 2.0 to 15kg and the chip was heated at about 12$0^{\circ}C$. In resin, the density of conductive particles coated with Au or Ni at the surface were 500, 1000, 2000 and 4000 particles/$\textrm{mm}^2$, and the diameter of particles were 5, 7 and 12${\mu}{\textrm}{m}$. As a result of the experiments, ACA process using ACA particle of diameter and density of 5${\mu}{\textrm}{m}$ and 4000 particles/$\textrm{mm}^2$ respectively shows optimum characteristic with the stabilzed bonding properties and contact resistance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.31-40
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• 2009

This paper presents a design of a high performance DC-DC boost converter as a power module for SOC designs. It applied to this chip that reduced inductor and capacitor for integrating on a chip, and it operates with a switching frequency of 100MHz. It has reliability and stability in high switching frequency. The controller of DC-DC boost converter is designed by voltage-mode control method and compensated properly. The designed DC-DC converter is fabricated with the 0.18${\mu}m$ standard CMOS technology with a thick-gate oxide option. The overall die size is 8.14$mm^2$, and controller size is 1.15$mm^2$. The converter has the maximum efficiency over 76% for the output voltage of 4V and load current larger 300mA. The load regulation is 0.012% (0.5mV) for the load current change of 100mA.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.4
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• pp.320-324
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• 2016

A new eccentric forging process for camber bolts has been suggested in this study. The camber bolt is manufactured by a two-step process: the typical forging process for normal bolts and the trimming process for the eccentric flange. The processes are performed under high forging load and generate a large amount of chip during trimming. A new forging process has been required in order to overcome these problems. The eccentric forging is the new process in which the load axis is offset from the central axis, as against central load applied in a typical forging process. The eccentric forging process could reduce forging load and save the amount of chip. In order to manufacture camber bolts by an optimum process, it is required to adjust the geometry of eccentric die and the offset from the central axis.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.43-46
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• 2001

This paper has been studied a implementation Home Automation by PLM and Telephone system. The PLM is composed of FSK IC-chip and the circuit for the power line communication. In this paper load control was made with PIC16F84A and its communication speed was 1200 baud rates.

• Journal of Information Display
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• v.6 no.4
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• pp.11-15
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• 2005

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.3
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• pp.66-74
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• 1997

In a high speed and high precision vertical machining center, chatter vibration is easily generated due to unbalanced masses in rotating parts and changtes of cutting forces. In this paper, modal test is performed to obtain modal parameters of the vertical machining center. In order to predit the cutting force of endmilling process for various cutting conditions, a mathematical model is given and this model is based on chip load, cutting geometry, and relationship between cutting forces and the chip load. Specific cutting constants of the model are obtained by averaging forces of cutting tests. The interactions between the dy- namic characteristics and cutting dynamics of the vertical machining center make the primary and the secondary feedback loops, and we make use of the equations of system to predict the chatter vibration. The chatter prediction is formulated as linear differential-differene equations, and simulated for several cases. Trends of vibration as radial and axial depths of cut are changed are shown and compared.

• Journal of Power Electronics
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• v.9 no.3
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• pp.507-515
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• 2009

This paper proposes an autonomous decentralized control for a parallel connected uninterruptible power supply (UPS) system based on a fast power detection method using a FPGA based hardware controller for a single phase system. Each UPS unit detects only its output voltage and current without communications signal exchange and a quasi dq transformation method is applied to detect the phase and amplitude of the output voltage and the output current for the single phase system. Fast power detection can be achieved based on a quasi dq transformation, which results in a realization of very fast transient response under rapid load change. In the proposed method, the entire control system is implemented in one FPGA chip. Complicated calculations are assigned to hardware calculation logic, and the parallel processing circuit makes it possible to realize minimized calculation time. Also, an Nios II CPU core is implemented in the same FPGA chip, and the software can be applied for non-time critical calculations. Applying this control system, an autonomous decentralized UPS system with very fast transient response is realized. Feasibility and stable operation are confirmed by means of an experimental setup with three UPSs connected in parallel. Also, rapid load change is applied and excellent performance of the system is confirmed in terms of transient response and stability.