• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.270-274
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• 2002

We have developed a new COG technique using flip chip solder joining technology for excellent resolution and high quality LCD panels. Using the eutectic Bi-Sn and the eutectic In-Ag solder bumps of 50-80 ${\mu}m$ pitch sizes, a ultrafine interconnection between IC and glass substrate was successfully made at or below $160^{\circ}C$. The contact resistance and reliability of Bi-Sn solder joint showed the superiority over the conventional ACF bonding.

• 설비공학논문집
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• 제7권2호
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• pp.266-275
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• 1995

A numerical investigation on the conduction-natural convection-surface radiation conjugate heat transfer in the enclosure having substrate and chips has been performed. A 2-dimensional simulation model is developed by considering heat transfer by conduction, convection and radiation. The solutions to the equation of radiative transfer are obtained by the discrete ordinates method using S-4 quadrature. The effects of Rayleigh number and the substrate-fluid thermal conductivity ratio on the cooling of chip are analyzed. The result shows that radiation is the dominant heat transfer mode in the enclosure.

• 마이크로전자및패키징학회지
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• 제19권1호
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• pp.25-32
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• 2012

Package for artificial satellite is to produce mass production for high package with reliability certification as well as develop SDRAM (synchronous dynamic RAM) module which has such as miniaturization, mass storage, and high reliability in space environment. It requires sophisticated technology with chip stacking or package stacking in order to increase up to 4Gbits or more for mass storage with space technology. To make it better, we should secure suitable processes by doing design, manufacture, and debugging. Pin type PCB substrate was then applied to QFP-Pin type 3D memory package fabrication. These results show that the 3D memory package for artificial satellite scheme is a promising candidate for the realization of our own domestic technologies.

• 한국전기전자재료학회논문지
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• 제34권1호
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• pp.8-15
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• 2021

Micro-LEDs can be applied to various parts of a product. However, it has disadvantages compared to general LEDs in large displays such as low efficiency, intensity, and contrast ratio, among others, owing to their short history of study. The simulations were carried out using ray-tracing software to investigate the change in light intensity and light distribution according to pattern shapes on the sapphire substrate of the flip-chip micro-LED (FC μ-LED) array. Three patterns-concave square patterns, convex square patterns, and Ag coated convex patterns-which existed on the opposite side of FC μ-LEDs (115 ㎛ × 115 ㎛) array, were applied. The intensity of FC μ-LEDs on the center of the receivers depends on the pattern depth with shape. The concave square patterns having FC μ-LEDs arrays show that decreasing intensity as the patterns depth. On the contrary, the convex square patterns having FC μ-LEDs arrays shows that increasing intensity as the patterns depth. In addition, the highest intensity shows that FC μ-LEDs having Ag-coated convex patterns on the opposite side of sapphire lead to a reduction in light crosstalk owing to the Ag film.

• 대한전자공학회논문지SD
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• 제45권4호
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• pp.131-136
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• 2008

[ $0.18-{\mu}m$ ] CMOS공정을 이용하여 근거리 무선통신(22-29 GHz)에서 응용할 수 있는 전력증폭기를 설계하였다. 전도성 기판에 의한 손실을 줄이기 위해서 기판 차폐된 두 가지 형태의 전송선로를 설계하고, 40 GHz 까지 측정 및 모델링하였다. 기판 차폐 microstrip line (MSL) 전송선로의 경우 27 GHz에서 약 0.5 dB/mm의 삽입손실을 나타내었다. 기판 차폐 MSL 구조를 이용한 전력증폭기는 0.83$mm^2$의 비교적 작은 면적을 차지하면서도 27 GHz에서 14.7 dB의 소신호 이득과 14.5 dBm의 출력을 나타내었다. 기판 차폐 coplanar waveguide (CPW) 전송선로의 경우 27 GHz에서 약 1.0 dB/mm 삽입손실을 나타내었으며, 이를 이용한 전력증폭기는 26.5 GHz에서 12 dB의 소신호 이득과 12.5 dBm의 출력을 나타내었다. 본 논문의 결과는 $0.18-{\mu}m$ CMOS공정을 이용한 저가격의 근거리 무선통신 시스템을 구현할 수 있는 가능성을 제시한다.

• 대한금속재료학회지
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• 제47권1호
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• pp.26-31
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• 2009

The effects of $Ar/O_2$ ion-beam pre-treatment conditions on the interfacial adhesion energy of sputterdeposited Cu thin film to FR-4 substrate were systematically investigated in order to understand the interfacial bonding mechanism for practical application to advanced chip-in-substrate package systems. Measured peel strength increases from $45.8{\pm}5.7g/mm$ to $61.3{\pm}2.4g/mm$ by $Ar/O_2$ ion-beam pre-treatment with anode voltage of 64 V. Interfacial bonding mechanism between sputter-deposited Cu film and FR-4 substrate seems to be dominated by chemical bonding effect rather than mechanical interlocking effect. It is found that chemical bonding intensity between carbon and oxygen at FR-4 surface increases due to $Ar/O_2$ ion-beam pretreatment, which seems to be related to the strong adhesion energy between sputter-deposited Cu film and FR-4 substrate.

• 마이크로전자및패키징학회지
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• 제7권2호
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• pp.47-53
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• 2000

TSM(Top Surface Metallurgy)이 증착된 유리기판의 Pb-free 솔더에 대한 젖음성을 무플럭스하에서 wetting balance법으로 평가하였다. TSM 층의 젖음성을 단면 증착시편의 wetting balance법으로부터 도출된 새로운 젖음성 지수들로 평가할 수 있었다. 유리기판의 TSM층으로는, Cu를 젖음층으로 하고 Au를 Cu의 산화 방지 층으로 사용하는 경우가 Au 자체를 젖음층으로 사용하는 경우보다 우수하였다. SnSb 솔더는 SnAg, SnBi, SnIn 솔더보다 TSM층에 대한 젖음특성이 우수하였다. 유리기판에 단면 증착된 TSM과 Pb-free솔더의 접촉각을 $F_{s}$와 기울어짐각을 측정하고, 메니스커스의 정적 상태에서 힘의 평형으로부터 유도된 식을 이용하여 계산할 수 있었다.

• 한국전산구조공학회:학술대회논문집
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• 한국전산구조공학회 1999년도 가을 학술발표회 논문집
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• pp.437-443
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• 1999

This paper deals with the stress singularity induced at the interface corner between the viscoelastic thin film and the rigid substrate subjected to uniform temperature change. The viscoelastic film has been assumed to be thermorheologically simple. The time-domain boundary element method(BEM) has been employed to investigate the behavior of interface stresses. The order of the free-edge singularity has been obtained numerically for a given viscoelastic model. It is shown that the free-edge stress intensity factor is relaxed with time, while the order of the singularity increases with time for the viscoelastic model considered.

• Transactions on Electrical and Electronic Materials
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• 제9권1호
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• pp.33-37
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• 2008

This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

• Journal of information and communication convergence engineering
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• 제13권2호
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• pp.81-85
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• 2015

A 94-GHz phased array antenna using a log-periodic antenna has been developed on a GaAs substrate. The developed phased array antenna comprises four log-periodic antennas, a phase shifter, and a Wilkinson power divider. This antenna was fabricated using the standard microwave monolithic integrated circuit (MMIC) process including an air bridge for unipolar circuit implementations on the same GaAs substrate. The total chip size of the fabricated phased array antenna is 4.8 mm × 4.5 mm. Measurement results showed that the fabricated phased array antenna had a very wide band performance from 80 GHz to 110 GHz with return loss characteristics better than -10 dB. In the center frequency of 94 GHz, the fabricated phased array antenna showed a return loss of -16 dB and a gain of 4.43 dBi. The developed antenna is expected to be widely applied in many applications at W-band frequency.