• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.59-63
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• 2013

In this paper, the impact of the copper densities of substrate layers on IC package warpage is studied experimentally and numerically. The substrate strips used in this study contained two metal layers, with the metal densities and patterns of these two layers varied to determine their impacts. Eight legs of substrate strips were prepared. Leg 1 to leg 5 were prepared with a HD (high density) type of strip and leg 6 to leg 8 were prepared with UHD (ultra high density) type of strip. The top copper metal layer was designed to feature meshed patterns and the bottom copper layer was designed to feature circular patterns. In order to consider the process factors, the warpage of the substrate bottom was measured step by step with the following manufacturing process: (a) bare substrate, (b) die attach, (c) applying mold compound (d) and post reflow. Furthermore, after the post reflow step, the substrate strips were diced to obtain unit packages and the warpage of the unit packages was measured to check the warpage trends and differences. The experimental results showed that the warpage trend is related to the copper densities. In addition to the experiments, a Finite Element Modeling (FEM) was used to simulate the warpage. The nonlinear material properties of mold compound, die attach, solder mask, and substrate core were included in the simulation. Through experiment and simulation, some observations were concluded.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.15-20
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• 2012

In electronics industry, the coming electronic devices will be expected to be high integration and convergence electronics. And also, it will be expected that the coming electronics will be flexible, bendable and wearable electronics. Therefore, the demands and interests of bonding technology between flexible substrate and chip for mobile electronics, e-paper etc. have been increased because of weight and flexibility of flexible substrate. Considering fine pitch for high density and thermal damage of flexible substrate during bonding process, the micro solder bump technology for high density and low temperature bonding process for reducing thermal damage will be required. In this study, we researched on bonding technology of chip and flexible substrate by using 25um Cu pillar bumps and Sn-Bi solder bumps were formed by electroplating. From the our study, we suggest technology on Cu pillar bump formation, Sn-Bi solder bump formation, and bonding process of chip and flexible substrate for the coming electronics.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.53-58
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• 2008

In this study, we fabricated embedded IC (Double Pole Double throw switch chip) polymer substrate and evaluate it for 2.4 GHz WiFi application. The switch chips were laminated using FR4 and ABF(Ajinomoto build up film) as dielectric layer. The embedded DPDT chip substrate were interconnected by laser via and Cu pattern plating process. DSC(Differenntial Scanning Calorimetry) analysis and SEM image was employed to calculate the amount of curing and examine surface roughness for optimization of chip embedding process. ABF showed maximum peel strength with Cu layer when the procuring was $80\sim90%$ completed and DPDT chip was laminated in a polymer substrate without void. An embedded chip substrate and wire-bonded chip on substrate were designed and fabricated. The characteristics of two modules were measured by s-parameters (S11; return loss and S21; insertion loss). Insertion loss is less than 0.55 dB in two presented embedded chip board and wire-bonded chip board. Return loss of an embedded chip board is better than 25 dB up to 6 GHz frequency range, whereas return loss of wire-bonding chip board is worse than 20 dB above 2.4 GHz frequency.

• Journal of the Korea Society for Simulation
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• v.26 no.1
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• pp.69-75
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• 2017

An MCP(Multi-chip Package) is a package consisting of several chips. Since several chips are stacked on the same substrate, multiple assembly steps are required to make an MCP. The characteristics of the chips in the MCP are dependent on the layer sequence. In the MCP manufacturing process, it is very essential to carefully consider the layer sequence in scheduling to achieve the intended throughput as well as the WIP balance. In this paper, we propose a scheduling methodology considering the layer sequence constraint.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.10
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• pp.676-681
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• 2015

Recently many studies being carried out to increase the light efficiency of LED. The external quantum efficiency of LED, generally the light efficiency, is determined by the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency of LED was already reached to more than 90%, but the light extraction efficiency is still insufficient compared with the internal quantum efficiency because the total internal reflection is generated in the interface between the LED chip and air. Thus, we studied about flip chip LED with PSS and performed the optical simulation which find more optimized PSS for flip chip LED to increase the light extraction efficiency. Decreasing of the total internal reflection and effect of diffused reflection according to PSS improved the light extraction efficiency. To get more higher the efficiency, we simulated flip chip with PSS that the parameters are arrangement, edge spacing, radius, height and shape of PSS.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.146-150
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• 2001

Microwave model and high-frequency measurement of the ACF flip-chip interconnection was investigated using a microwave network analysis. S-parameters of on-chip and substrate were separately measured in the frequency range of 200 MHz to 20 GHz using a microwave network analyzer HP8510 and cascade probe. And the cascade transmission matrix conversion was performed. The same measurements and conversion techniques were conducted on the assembled test chip and substrate at the same frequency range. Then impedance values in ACF flip-chip interconnection were extracted from cascade transmission matrix. ACF flip chip interconnection has only below 0.1nH, and very stable up to 13 GHz. Over the 13 GHz, there was significant loss because of epoxy capacitance of ACF. However, the addition of SiO$_2$filler to the ACF lowered the dielectric constant of the ACF materials resulting in an increase of resonance frequency up to 15 GHz. High frequency behavior of metal Au stud bumps was investigated. The resonance frequency of the metal stud bump interconnects is higher than that of ACF flip-chip interconnects and is not observed at the microwave frequency band. The extracted model parameters of adhesive flip chip interconnects were analyzed with the considerations of the characteristics of material and the design guideline of ACA flip chip for high frequency applications was provided.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• Journal of the Semiconductor & Display Technology
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• v.1 no.1
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• pp.29-33
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• 2002

In the flip-chip process, the problem like electric defect or fatigue crack caused by the difference of CTE, between chip and substrate board had occurred. Underfill of flip chip to overcome this defects is noticed as important work developing in whole reliability of chip by protecting the chip against the external shock. In this paper, we introduce the underfill methods using mold and plunge and improvement of process and reliability, and the advantage which can be taken from embodiment of device.

• Korean Journal of Optics and Photonics
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• v.19 no.5
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• pp.381-385
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• 2008

We have analyzed the effect of the substrate removal and packaging schemes on light output characteristics in InGaN/Sapphire LEDs. The removal of the sapphire substrate helps to dissipate the heat generated in the junction, but the advantage comes only with the detrimental effect of degrading the photon extraction efficiency. If the substrate-removed chip is attached to a metallic mount with good thermal conductivity, the maximum driving current is increased drastically, producing significantly increased light output and therefore compensating the photon extraction efficiency degradation. On a dielectric mount with a relatively poor thermal conductivity, however, it produces smaller light output, over most input current range, than the regular type of chips with the sapphire substrate remaining. Thus, for low power applications, the regular chips may be preferred over the substrate-removed chips, regardless of the chip mounts employed.

• Journal of the Korean Physical Society
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• v.73 no.9
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• pp.1346-1350
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• 2018

An electrode-evaporation technology on both the top and bottom sides of the bare vertical-type single chip separated from the traditional substrate by cooling, was developed for III-nitride vertical-type single chip LEDs with thick GaN epilayer. The post-process of the cooling step was followed by sorting the bare vertical-type single chip LEDs into the holes in a pocket-type shadow mask for deposition of the electrodes at the top and bottom sides of bare vertical-type single chip LEDs without the traditional substrate for electrode evaporation technology for vertical-type single chip LEDs. The variation in size of the hole between the designed shadow mask and the deposited electrodes owing to the use of the designed pocket-type shadow mask is investigated. Furthermore, the electrical and the optical properties of bare vertical-type single chip LEDs deposited with two different shapes of n-type electrodes using the pocket-type shadow mask are investigated to explore the possibility of the e-beam evaporation method.