• 전자공학회논문지C
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• 제35C권2호
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• 전기전자학회논문지
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• 제1권1호
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• pp.1-10
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• 1997

It is well-known that rectangular bulk-Si sensors prepared by etch or epi etch-stop micromachining technology are already in practical use today, but the conventional bulk-Si sensor shows some drawbacks such as large chip size and limited applications as silicon sensor device is to be miniaturized. We consider a circular-shape SOI(Silicon-On-Insulator) micro-cavity technology to facilitate multiple sensors on very small chip, to make device easier to package than conventional sensor like pressure sensor and to provide very high over-pressure capability. This paper demonstrates the cross-functional results for stress analyses(targeting $5{\mu}m$ deflection and 100MPa stress as maximum at various applicable pressure ranges), for finding permissible diaphragm dimension by output sensitivity, and piezoresistive sensor theory from two-type SOI structures where the double SOI structure shows the most feasible deflection and small stress at various ambient pressures. Those results can be compared with the ones of circular-shape bulk-Si based sensor$^{[17]}. The SOI micro-cavity formed the sensors is promising to integrate with calibration, gain stage and controller unit plus high current/high voltage CMOS drivers onto monolithic chip.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.21-24
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• 2000

This paper introduces the design and implementation of a Ku-band 5-bit monolithic phase shifter with a ceramic package. The 5-bit phase shifter MMIC was designed and fabricated by using GaAs MESFET switches. The packaged phase shifter demonstrates a phase error less than 11.3 $^{\circ}$ RMS and an insertion loss variation less than 1.0㏈ RMS for 13∼15㎓. For all 32 states, an insertion loss is measured to be 12.2${\pm}$2.2㏈, an input return loss more than 5.0㏈, and an output return loss more than 6.2㏈ from 13㎓ to 15㎓. The chip size of the 5-bit phase shifter MMIC is 2.35${\times}$1.65mm$\^$2/ including digital control circuits. The size of the ceramic packaged phase shifter is 7.2${\times}$6.2mm$\^$2/.

• 한국정밀공학회지
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• 제29권5호
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• pp.563-571
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• 2012

In 3D integration package using TSV technology, bonding is the core technology for stacking and interconnecting the chips or wafers. During bonding process, however, warpage and high stress are introduced, and will lead to the misalignment problem between two chips being bonded and failure of the chips. In this paper, a finite element approach is used to predict the warpages and stresses during the bonding process. In particular, in-plane deformation which directly affects the bonding misalignment is closely analyzed. Three types of bonding technology, which are Sn-Ag solder bonding, Cu-Cu direct bonding and SiO2 direct bonding, are compared. Numerical analysis indicates that warpage and stress are accumulated and become larger for each bonding step. In-plane deformation is much larger than out-of-plane deformation during bonding process. Cu-Cu bonding shows the largest warpage, while SiO2 direct bonding shows the smallest warpage. For stress, Sn-Ag solder bonding shows the largest stress, while Cu-Cu bonding shows the smallest. The stress is mainly concentrated at the interface between the via hole and silicon chip or via hole and bonding area. Misalignment induced during Cu-Cu and Sn-Ag solder bonding is equal to or larger than the size of via diameter, therefore should be reduced by lowering bonding temperature and proper selection of package materials.

• 한국생산제조학회지
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• 제23권6호
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• pp.609-617
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• 2014

We have studied a chip-on-board LED lighting optical system for various luminous-intensity-distribution angles of the LED. An optical system that can accept different LEDs was made to reduce the systems's weight and size as we selected the chip-on-board LED, which is easy to apply to optical systems, unlike existing package-on-board LEDs. The luminous-intensity-distribution angles were $45^{\circ}$, $60^{\circ}$, $90^{\circ}$, and $120^{\circ}$. We researched these four types of optical systems. The $45^{\circ}$ and $60^{\circ}$ units were developed into reflectors, and the $90^{\circ}$ and $120^{\circ}$ units, into lenses. We checked the performance of the designed optical system through simulation and made a mock-up. Then we made a prototype of the chip-on-board LED high bay for use with the mock-up. After measuring its performance, we tested the luminous-intensity-distribution angles and compared them with simulation data. The resulting prototype was developed considering brightness, light uniformity, age, and economics which are suitable for a factory environment.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.205-208
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• 2001

Steady state and transient thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage for microwave oven. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally copper wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin and epoxy with a thickness of $25{\mu}m$ and $3700{\mu}m$, respectively. The chip size, thickness and material properties were very important factor for high voltage diode package. And also, thermal stress value was highest in the edge of diode and solder. So, design of edge in silicon was very important to thermal stress.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.205-208
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• 2001

Steady state and transient thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage for microwave oven. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally copper wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin and epoxy with a thickness of 25$\mu\textrm{m}$ and 3,700$\mu\textrm{m}$, respectively. The chip size, thickness and material properties were very important factor for high voltage diode package. And also, thermal stress value was highest in the edge of diode and solder. So, design of edge in silicon was very important to thermal stress.

• 한국광학회지
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• 제16권4호
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• pp.345-353
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• 2005

포토 다이오드(photodiode) 조정 방식을 이용해서, 비전 시스템을 장착한 고가의 정밀 자동 조립조정 장비 없이 홀로그램 픽업 모듈을 제작하는 새로운 방법을 제안하였다. 저가격화를 위해서 리드 프레임형의 반도체 레이저와 COB(Chip on Board)형의 포토 다이오드를 사용했고, 초점 에러 신호(focus error, FES) 검출방법은 스팟 사이즈 검출법(spot size detection, SSD), 트랙 에러 신호(tracking error, TES) 검출방법은 삼빔법(3 beam method)을 이용했다. 이를 만족하는 픽업 홀로그램 모듈 광학계를 설계하고, 조립조정 프로세스 수립 및 시스템을 제작하였으며, 조립된 홀로그램 모듈을 이용하여 CD에서 데이터를 검출하는 실험을 통해 제안된 포토 다이오드 조정방식의 유용함을 입증하였다.

• 한국전기전자재료학회논문지
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• 제21권3호
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• pp.265-271
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• 2008

TCP(Tape Carrier Package), COG (Chip On Glass), COF(Chip On Film) are three methods for connecting LDI(LCD Driver IC) with LCD panels. Especially COF is growing its portion of market place because of low cost and fine pitch correspondence. But COF has a problem of the lead broken failure in LCD module process and the usage of customer. During PCB (Printed Circuit Board) bonding process, the mismatch of the coefficient of thermal expansion between PCB and D-IC makes stress-concentration in COF lead, and also D-IC bending process during module assembly process makes the level of stress in COF lead higher. As an affecting factors of lead-broken failure, the effects of SR(Solder Resister) coating on the COF lead, surface roughness and grain size of COF lead, PI(Polyimide) film thickness, lead width and the ACF(Anisotropic Conductive Film) overlap were studied, The optimization of these affecting manufacturing processes and materials were suggested and verified to prevent the lead-broken failure.

• 반도체디스플레이기술학회지
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• 제10권4호
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• pp.37-42
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• 2011

In this paper, novel carbon nanotube (CNT)-filled Solderable electrically conductive adhesive (ECA) and joining process have been developed. To investigate the bonding characteristics of CNT-filled Solderable ECA, three types of Solderable ECAs with different CNT weight percent (0, 0.1, 1wt%) were formulated. For a joining process, the quad flat package (QFP) chip was used. The QFP chip had a size of $14{\times}14{\times}2.7$ mm and a 1 mm lead pitch. The test board had a Cu daisy-chained pattern with 18 ${\mu}m$ thick. After the bonding process, the bonding characteristics such as morphology of conduction path, electrical resistance and pull strength were measured for each formulated ECAs. As a result, the electrical and mechanical bonding characteristics for a QFP joints using CNT-filled ECA were improved about 10% compared to those of QFP joints using ECA without CNT.