• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.259-268
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• 2008

Multi-Core processors have become main-stream microprocessors in recent years. Servers based on these multi-core processors are widely adopted in High Performance Computing (HPC) and commercial business applications as well. These servers provide increased level of parallelism, thus can potentially boost the performance for applications. However, the shared resources among multiple cores on the same chip can become hot spots and act as performance bottlenecks. Therefore it is essential to optimize the use of shared resources for high performance and scalability for the multi-core servers. In this paper, we conduct experimental studies to analyze the positive and negative effects of the resource sharing on the performance of HPC applications. Through the analyses we also characterize the performance of multi-core servers.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.463-467
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• 2000

In this paper, we have implemented the Web Server Patient Monitoring System using PPP. It is composed of two parts. The first part is the Analog board for acquiring ECG signals. The second part is the module for processing and transmitting the acquired signal. The second part is using PPP for dial-up networking, TCP/IP for Internet, HTTP for web browser and JAVA program for a Patient Monitoring Program in one chip. In home, it is not need to establish another network line because it uses a telephone line. And a user who want to monitor a patient's biosignal can monitor a patient without wholly open network because it is the network sewer. The Patient Monitoring Program runs on a web browser by downloaded JAVA codes when a user connect to this system. It can make the Home Patient Monitoring Program decrease cost. It can help to avoid the limitation of monitoring a patient.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2601-2606
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• 2012

In this paper, an electricity management system, which saves energy by utilizing electricity consumption of load from an environment that uses at least two compact generators, is proposed and developed. A hardware is constructed by using TMS320C6713 DSP chip made by TI that is capable of high speed hardware floating point processing while serial communication is used for communication with a monitoring PC. Manual control is made possible from the monitoring PC and automatic on/off is enabled in the generator by using data collected by CT/PT sensor from the DSP mainboard. Test results confirm that the electricity management system proposed in this study functions without abnormality. The application of an algorithm that saves energy by using electricity consumption of load also allows for a longer supply of electricity compared to continuously using two compact generators.

• The KIPS Transactions:PartB
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• v.9B no.4
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• pp.429-436
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• 2002

In order to apply the artificial neural network to the practical application, it is needed to implement it with the hardware system. It is most promising to make it with the hybrid VLSI among various possible technologies. When we Implement a trained network into the hybrid neuro-chips, it is to be performed the process of the quantization on its neuron outputs and its weights. Unfortunately this process cause the network's outputs to be distorted from the original trained outputs. In this paper we analysed in detail the statistical characteristics of the distortion. The analysis implies that the network is to be trained using the normalized input patterns and finally into the solution with the small weights to reduce the distortion of the network's outputs. We performed the experiment on an application in the time series prediction area to investigate the effectiveness of the results of the analysis. The experiment showed that the network by our method has more smaller distortion compared with the regular network.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.389-396
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• 2003

InfiniBand technology is being accepted as the future system interconnect to serve as the high-end enterprise fabric for cluster computing. This paper presents the design and implementation of the InfiniBand system interconnect, focusing on an InfiniBand host channel adapter (HCA) based on dual ARM9 processor cores The HCA is an SoC tailed KinCA which connects a host node onto the InfiniBand network both in hardware and in software. Since the ARM9 processor core does not provide necessary features for multiprocessor configuration, novel inter-processor communication and interrupt mechanisms between the two processors were designed and embedded within the KinCA chip. Kinch was fabricated as a 564-pin enhanced BGA (Bail Grid Array) device using 0.18${\mu}{\textrm}{m}$ CMOS technology Mounted on host nodes, it provides 10 Gbps outbound and inbound channels for transmit and receive, respectively, resulting in a high-performance cluster system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.451-459
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• 2007

RFID it reads information which is it writes, the semiconductor chip for and the radio frequency system which uses the hazard antenna it has built-in transmission of information it talks. Formation which is transmitted like this collection and America which it filtrates wey the RFID search service back to inform the location of the server which has commodity information which relates with an object past record server. The hazard where measurement analysis result the leader for electronic interference does not occur consequently together from with verification test the power level which is received from the antenna grade where it stands must maintain minimum -55dBm and the electronic interference will not occur with the fact that, antenna and reel his recognition distance the maximum 7m until the recognition which is possible but smooth hazard it must stand and and with the fact that it will do from within and and and 3-4m it must be used Jig it is thought.

• KIPS Transactions on Software and Data Engineering
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• v.4 no.2
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• pp.65-70
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• 2015

In the PCB(Printed Circuit Board) manufacturing industry, the yield is an important management factor because it affects the product cost and quality significantly. In real situation, it is very hard to ensure a high yield in a manufacturing shop because products called chips are made through hundreds of nano-scale manufacturing processes. Therefore, in order to improve the yield, it is necessary to analyze main fault process and equipment that cause low PCB yield. This paper proposes a systematic approach to discover fault-causing processes and equipment by using a logistic regression and a stepwise variable selection procedure. We tested our approach with lot trace records of real work-site. A lot trace record consists of the equipment sequence that the lot passed through and the number of faults for each fault type in the lot. We demonstrated that the test results reflected the real situation of a PCB manufacturing line.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.59-64
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• 2006

The slope of the ramp generator in a single slope ADC(analog-to-digital converter) suffers from process and frequency variation. This variation in ramp slope causes ADC gain variation and eventually limits the performance of the ISP(image signal processing) in a CIS(CMOS image sensor) that uses the single slope ADC. This paper proposes a ramp slope BISC(built-in-self-calibration) scheme for CIS. The CIS with proposed BISC was fabricated with a $0.35{\mu}m$ process. The measurement results show that the proposed architecture effectively calibrate the ramp slope against process and clock frequency variation. The silicon area overhead is less than $0.7\%$ of the full chip area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.45-53
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• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

• Convergence Security Journal
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• v.15 no.2
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• pp.3-9
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• 2015

The development of the digital compression technology and the broadcasting receiver's processing power make it possible to apply a multi-view function to the broadcasting services. The multi-view function is usually utilized to provide simultaneously several programs to viewers or to implement a multi-angle service of a sports program that allows a viewer to choose a video of his/her prefer viewpoint. The paper proposes an integrated method for utilizing a multi-view function in the digital broadcasting environment in which more than 100 programs are on air and there may be various data services which want to use multi-view video clips. For the purpose, a method of composing and transmitting multi-view videos and related information has been devised and a Java API to utilize the rapid editing function of a decoding chip-set has been implemented to clip, resize, and display parts of the multi-view videos.