• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.89-97
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• 2008

Chaotic behavior in motor systems is undesired dynamics in real-time implementation since the speed is oscillated in a wide range and the torque is changed by a random manner. We present an adaptive control approach for time-varying permanent-magnet synchronous motors (PMSM) with chaotic phenomenon. We consider that its parameters are changed randomly within certain bounds. First, a nonlinear system model of a PMSM is transformed to derive a nominal linear control strategy. Then, an auxiliary control for compensating real-time control error occurred by system perturbation due to parameter change is designed by using Lyapunov stability theory. Numerical simulation is accomplished for evaluating its efficiency and reliability comparing with the traditional control method. Additionally, we test our control method in real-time motor experiment including a PSoC based drive system to demonstrate its practical applicability.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.65-71
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• 2005

Physical signals generated in the real world are transformed into electrical signals through sensors and fed into electronic circuits. The electrical signals input to electronic circuits are in analog form, thus they must be converted to digital signals using an ADC(Analog-Digital Converter) for digital processing. Signal processing circuits and ADCs that are to be integrated on a single chip together with silicon micro sensors should be designed to have less silicon area and less power consumption. This paper proposed a charge redistribution ADC which reduces silicon area considerably. The proposed method achieves 8 bit conversion by performing 4-bit conversion twice. It reduced the area of capacitor array, which takes most of the ADC area, by 1/16 when compared to a conventional method. Though it uses twice the number of clocks as a conventional method, it would be appropriate to be integrated with a silicon pressure sensor on a single chip since it does not demand high conversion rate.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.215-223
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• 2000

The advancements in technology which have lead to higher and higher levels of integration have required advancements in the methods used in designing VLSI chip. A key to enable a complicated chip design is the use of hierarchy in the design process. Hierarchy organizes the function of a large number of transistors ito a particular, easy-to-manage function. For these reasons, hierarchy has been used in the design process of digital functions for many years. However, there exists differences in a design analysis phase, especially in timing analysis, due to multiple views for the same design. In timing analysis of the hierarchical design, every path is analyzed within partitioned modules independently and the global timing analysis is applied to the whole design considering each module as a single timing component. Therefore, timing results of the hierarchical design could not be same as those of non-hierarchical flat design. In this paper, we formulate the timing problem in the hierarchical design and analyze the possible source of timing differences. We define a new terminology of "consistent result" between different views for the same design. We also propose a new partitioning algorithm to obtain the consistent results. This algorithm helps to enhance the design cycle time.

• Journal of Information Processing Systems
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• v.8 no.2
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• pp.347-358
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• 2012

Recently, security researches have been processed on the method to cover a broader range of hacking attacks at the low level in the perspective of hardware. This system security applies not only to individuals' computer systems but also to cloud environments. "Cloud" concerns operations on the web. Therefore it is exposed to a lot of risks and the security of its spaces where data is stored is vulnerable. Accordingly, in order to reduce threat factors to security, the TCG proposed a highly reliable platform based on a semiconductor-chip, the TPM. However, there have been no technologies up to date that enables a real-time visual monitoring of the security status of a PC that is operated based on the TPM. And the TPB has provided the function in a visual method to monitor system status and resources only for the system behavior of a single host. Therefore, this paper will propose a m-TMS (Mobile Trusted Monitoring System) that monitors the trusted state of a computing environment in which a TPM chip-based TPB is mounted and the current status of its system resources in a mobile device environment resulting from the development of network service technology. The m-TMS is provided to users so that system resources of CPU, RAM, and process, which are the monitoring objects in a computer system, may be monitored. Moreover, converting and detouring single entities like a PC or target addresses, which are attack pattern methods that pose a threat to the computer system security, are combined. The branch instruction trace function is monitored using a BiT Profiling tool through which processes attacked or those suspected of being attacked may be traced, thereby enabling users to actively respond.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.69-72
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• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.3
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• pp.7-14
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• 2003

MPEG-1 audio standard is the algorithm for the compression of high-qualify digital audio signals. The standard dictates the functions of encoder and decoder pair, and includes three different layers as the complexity and the performance of the encoder and decoder. In this paper, we implemented the real-time system of MPEG-1 audio layer III decoder(MP3) with the TMS320C541 fixed point DSP chip. MP3 algorithm uses psycho-acoustic characteristic of human hearing system, and it reduces the amount of data with eliminating the signals hard to be heard to the hearing system of human being. It is difficult to implement MP3 decoder with fixed Point DSP because of it's broad dynamic range. We implemented realtime system with fixed DSP chip by using weighted look-up tables to reduce the amount of calculation and solve the problem of broad dynamic range.

• Journal of the Korean Society for Nondestructive Testing
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• v.20 no.6
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• pp.511-520
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• 2000

Ultrasonic pulse echo method comes to be difficult to apply to the multi-layered structure with very thin layer, because the echoes from the top and the bottom of the layer are superimposed. We can easily meet this problem when the silicon chip layer in the semiconductor is inspected by a SAM equipment using fairly low frequency lower than 20MHz by which severe attenuation in the epoxy mold compound of packaging material can be overcome. Conventionally, deconvolution technique has been used for the decomposition of superimposed UT signals, however it has disabilities when the waveform of the transmitted signal is distorted according to the propagation. In this paper, the wavelet transform based deconvolution(WTBD) technique is proposed as a new signal processing method that can decompose the superimposed echo signals with superior performances compared to the conventional deconvolution technique. WTBD method uses the wavelet transform in the pre-stage of deconvolution to extract out the common waveform from the transmitted and received signal with distortion. Performances of the proposed method we shown by through computer simulations using model signal with noise and we demonstrated by through experiments for the fabricated semiconductor sample with partial delamination at the top of silicon chip layer.

• Composites Research
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• v.34 no.1
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• pp.70-75
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• 2021

This paper presents a novel algorithm to reconstruct meso-scale representative volume elements (RVE), referring to experimentally observed features of Sheet Molding Compound (SMC) composites. Predicting anisotropic mechanical properties of SMC composites is challenging in the multiscale virtual test using finite element (FE) models. To this end, an SMC RVE modeler consisting of a series of image processing techniques, the novel reconstruction algorithm, and a FE mesh generator for the SMC composites are developed. First, micro-CT image processing is conducted to estimate probabilistic distributions of two critical features, such as fiber chip orientation and distribution that are highly related to mechanical performance. Second, a reconstruction algorithm for 3D fiber chip packing is developed in consideration of the overlapping effect between fiber chips. Third, the macro-scale behavior of the SMC is predicted by the multiscale analysis.

• The KIPS Transactions:PartC
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• v.19C no.3
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• pp.179-184
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• 2012

Due to the absence of an alternative algorithm SHA-2, NIST (National Institute of Standards and Technology) is proceeding to development project of SHA-3. NIST announced five candidates of the final round at the end of 2010. Side-channel attack scenarios of five candidates for SHA-3 final round have been proposed. In this paper, we prove the possibility of the analysis against 32-bit modular addition by 8-bit blocks from our experiment on ARM chip board with a register size of 32-bit. In total we required 9700 power traces to successfully recover the 128-bit secret key for the attack against.

• Journal of electromagnetic engineering and science
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• v.12 no.4
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• pp.234-239
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• 2012

This paper presents a compact K-band Doppler radar sensor for human vital signal detection that uses a radar configuration with only single coupler. The proposed radar front-end configuration can reduce the chip size and the additional RF power loss. The radar front-end IC is composed of a Lange coupler, VCO, and single balanced mixer. The oscillation frequency of the VCO is from 27.3 to 27.8 GHz. The phase noise of the VCO is -91.2 dBc/Hz at a 1 MHz offset frequency, and the output power is -4.8 dBm. The conversion gain of the mixer is about 11 dB. The chip size is $0.89{\times}1.47mm^2$. The compact Ka-band Doppler radar system was developed in order to demonstrate remote human vital signal detection. The radar system consists of a Ka-band Doppler radar module with a $2{\times}2$ patch array antenna, baseband signal conditioning block, DAQ system, and signal processing program. The front-end module size is $2.5{\times}2.5cm^2$. The proposed radar sensor can properly capture a human heartbeat and respiration rate at the distance of 50 cm.