• Journal of the Korean Association of Geographic Information Studies
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• v.7 no.4
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• pp.15-23
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• 2004

In order to utilize remote sensed images effectively, it is necessary to correct geometric distortion. Geometric correction is a critical step to remove geometric distortions in satellite images. For geometric correction, Ground Control Points (GCPs) have to be chosen carefully to guarantee the quality of geocoded satellite images, digital maps, GPS surveying or other data. Traditional approach to geometric correction used GCPs requires substantial human operations. Also that is necessary much time and manpower. In this paper, we presented an on-line automatic geometric correction by constructing GCP Chip database. The Proposed on-line automatic geometric correction system is consists of four part. Input image, control the GCP Chip, revision of selected GCP, and output setting part. In conclusion, developed system reduced the processing time and energy for tedious manual geometric correction and promoted usage of Landsat imagery.

• ETRI Journal
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• v.38 no.5
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• pp.981-987
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• 2016

We present a cost-effective dual polarization quadrature phase-shift coherent receiver module using a silica planar lightwave circuit (PLC) hybrid assembly. Two polarization beam splitters and two $90^{\circ}$ optical hybrids are monolithically integrated in one silica PLC chip with an index contrast of $2%-{\Delta}$. Two four-channel spot-size converter integrated waveguide-photodetector (PD) arrays are bonded on PD carriers for transverse-electric/transverse-magnetic polarization, and butt-coupled to a polished facet of the PLC using a simple chip-to-chip bonding method. Instead of a ceramic sub-mount, a low-cost printed circuit board is applied in the module. A stepped CuW block is used to dissipate the heat generated from trans-impedance amplifiers and to vertically align RF transmission lines. The fabricated coherent receiver shows a 3-dB bandwidth of 26 GHz and a common mode rejection ratio of 16 dB at 22 GHz for a local oscillator optical input. A bit error rate of $8.3{\times}10^{-11}$ is achieved at a 112-Gbps back-to-back transmission with off-line digital signal processing.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.344-352
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• 2020

Covertness and performance are very important design goals in the underwater communications. To satisfy both of them, we proposed efficient underwater communication model which combined multiband and direct sequence spread spectrum method in order to improve performance and covertness simultaneously. Turbo coding method with 1/3 coding rates is used for channel coding algorithm, and turbo equalization method which iterately exchange probabilistic information between equalizer and decoder is used for receiver side. After optimal threshold value was set in Rake processing, this paper analyzed the performance by varying the number of chips were 8, 16, 32 and the number of bands were from 1 to 4. Through the simulation results, we confirmed that the performance improvement was obtained by increasing the number of bands and chips. 2~3 dB of performance gain was obtained when the number of chips were increased in same number of bands.

• The KIPS Transactions:PartC
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• v.19C no.1
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• pp.39-46
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• 2012

In this paper, we propose a key distribution scheme for flexible chipset pairing conditional access system. Chipset pairing conditional access system is the implementation of CA (Conditional Access) module by using both embedded secure chip in a Set-Top Box(STB) and smartcard, and the secure chip embedded in a STB forms a secure channel between the smartcard and the STB. In short, it is the system that a smartcard outputs encrypted CW (Control Word) to the STB, and the STB decrypts an encrypted CW by using the embedded secure chip. The drawback of this chipset pairing conditional access system is that one smartcard is able to be used for only one specified STB since it is the system using the STB bound to a smartcard. However, the key distribution scheme proposed in this paper overcomes a drawback of current chipset pairing conditional access system by using Chinese Remainder Theorem(CRT). To be specific, with this scheme, one smartcard can be used for multiple, not single, STBs, and applied to current chipset pairing without great changes.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.347-352
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• 2005

유비쿼터스라는 새로움 페러다임의 도래로 인해 많은 IT산업이 이를 중심으로 많은 발전을 하고 있다. 이러한 유비쿼터스 관련 산업에 있어서 상당 부분 무선 통신기술인 RF를 기반으로 하고 있으며, 이를 활용하여 RFID 시스템 및 센서 네트워크 등이 발전하고 있는 추세이다. 본 논문에서 이러한 무선 통신기술에 적합한 저전력 저전압 Wireless UHF 트렌시버인 CC1020 칩을 이용하여 무선통신시스템을 구현하였다. 이 시스템을 제어하기 위해 MCU와의 Interface를 구성하고 CC1020 칩의 레지스터를 설정하기 위해 4선의 직렬 구성 인터페이스로 모토로라사에서 개발된 근거리용 고속 직렬 동기식 통신규격인 SPI 방식을 이용하였다. 따라서 레지스터 종류 및 설정순서와 타이밍에 대한 내용과 MCU와의 인터페이스 중심으로 설명하였으며, 시스템을 구현하고 실험을 통해 신호의 파형과 데이터 송수신을 확인하였다.

• ETRI Journal
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• v.31 no.5
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• pp.510-517
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• 2009

A high throughput parallel decoding method is developed for context-based adaptive variable length codes. In this paper, several new design ideas are devised and implemented for scalable parallel processing, a reduction in area, and a reduction in power requirements. First, simplified logical operations instead of memory lookups are used for parallel processing. Second, the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of the input stream can be analyzed simultaneously. For comparison, we designed a logical-operation-based parallel decoder for M=8 and a conventional parallel decoder. High-speed parallel decoding becomes possible with our method. In addition, for similar decoding rates (1.57 codes/cycle for M=8), our new approach uses 46% less chip area than the conventional method.

• ETRI Journal
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• v.42 no.4
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• pp.534-548
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• 2020

This study presents a new architecture for a field programmable analog array (FPAA) for use in low-frequency applications, and a generalized circuit realization method for the implementation of nth-order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA-C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA-C symmetric balanced structure for even/odd-nth-order low-pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90-nm complementary metal-oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low-power designs for implementation of biopotential signal processing systems.

• Korea-Australia Rheology Journal
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• v.21 no.2
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• pp.83-89
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• 2009

Coating process plays an important role in information technology such as display, battery, chip manufacturing and so on. However, due to complexity of coating material and fast deformation of the coating flow, the process is hard to control and it is difficult to maintain the desired quality of the products. Moreover, it is hard to measure the coating process because of severe processing conditions such as high drying temperature, high deformation coating flow, and sensitivity to the processing variables etc. In this article, the coating process is to be re-illuminated from the rheological perspectives. The practical approach to analyze and quantify the coating process is discussed with respect to coating materials, coating flow and drying process. The ideas on the rheology control of coating materials, pressure and wet thickness control in patch coating process, and stress measurement during drying process will be discussed.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.4
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• pp.156-163
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• 1996

In this paper, we described the implementation and the sound quality assessment of a real-time stereo audio codec using TMS320C40 DSP (digital signal processing) chip for low bitrte and high quality audio. We implemented hardware and software in order to overcome a real-time processing problem of audio compression algorithm that can be produced by largely recursive computing and complexity of the process. We have studied five types of distortion that can be produced by perceptual coding and the codec was evaluated by eight test musics that are selected in SQAM (sound quality assessment material) 422-2-4-2 produced by EBU (european broadcast union). The subjective listening tests were carried out on the codec quality and preformance by double blind method in a listening room with eleven listeners. As a result, 5 grade-impairment scale was scored under minus one and the codec quality was evaluated to be perceptible, but not annoying.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.2
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.