• Journal of Welding and Joining
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• v.33 no.5
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• pp.41-46
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• 2015

The snap cure NCP(non-conducive paste) adhesive material is essentially required for the high productivity flip chip bonding process. In this study, the accessibility of DEA(dielectric analysis) method for the evaluation of snap cure behavior was investigated with comparison to the isothermal DSC(differential scanning calorimetry) method. NCP adhesive was mainly formulated with epoxy resin and imidazole curing agent. Even though there were some noise in the dielectric loss factor curve measured by DEA, the cure start and completion points could be specified clearly through the data processing of cumulation and deviation method. Degree of cure by DEA method which was measured from the variation of the dielectric loss factor of adhesive material was corresponded to about 80% of the degree of cure by DSC method which was measured from the heat of curing reaction. Because the adhesive joint cured to the degree of 80% in the view point of chemical reaction reveals the sufficient mechanical strength, DEA method is expected to be used effectively in the estimation of the high speed curing behavior of snap cure type NCP adhesive material for flip chip bonding.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.65-71
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• 2022

In the case of Mobile PKG Trend is in a situation where a decrease in Mold Top Margin is inevitable due to its miniaturization and high capacity product requirements. However, conventional laser marking technology has an average depth of deep, and when applied to narrow top margin products, PKG strength is expected to decrease due to overlapping processing, and reliability is reduced due to poor quality such as chip damage due to laser exposure. Therefore, we have secured the technology through research on low-depth laser marking solutions that can accommodate narrow top margin products. As a result of the evaluation of applicable technology application for PKG development products, it was verified that the marking depth decreased by 67% reduced and the PKG strength increased by 12%. Furthermore, the quality verification of Laser Damage that can occur through PKG Mechanical analysis was performed, and no Chip Damage defects were found. This ensured the stability of mass production application quality.

• Clean Technology
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• v.27 no.3
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• pp.240-246
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• 2021

The waste etching solution for chip on film (COF) contained about 3.5% copper, and it was recovered through cementation using iron samples. The effect of cementation with plate, chip, and powder iron samples was investigated. The molar ratio (m/r) of iron to copper was used as a variable in order to increase the recovery rate of copper. As the molar ratio increased, the copper content in the solution rapidly decreased at the beginning of the cementation reaction. Before and after the reaction, the copper content of the solution was determined by Inductively Coupled Plasma (ICP) using copper concentration according to time. After cementation at room temperature for 1 hour, the recovery rate of copper had increased the most in the iron powder sample, having the largest specific surface area of the samples, followed by the chip and plate samples. The recovered copper powder was characterized for its crystalline phase, morphology, and elemental composition by X-ray diffraction (XRD), scanning electron microscopy (SEM), and Energy-dispersive X-ray spectroscopy (EDS), respectively. Copper and unreacted iron were present together in the iron powder samples. The optimum condition for recovering copper was obtained using iron chips with a molar ratio of iron to copper of 4 giving a recovery rate of about 98.4%.

• 전기의세계
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• v.38 no.7
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• pp.46-52
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• 1989

지금까지 Vector supercomputer를 비롯한 여러종류의 supercomputer의 기술발전 추세를 간단히 살펴보았다. 앞으로의 Supercomputer는 VLSI기술의 발달, GaAs같은 새로운 소재의 chip, optical connection을 이용한 더 나은 Package방식, 보다 큰 memory 그리고 parallel processing을 최대한 이용하여 현재의 supercomputer성능보다 엄청나게 강력한 Test FLOPS급의 성능을 발휘할 것으로 기대된다. 또한 전문분야별 Supercomputer들도 발전을 거듭하면서 성능은 크게 증가하고 값은 떨어져서 과학기술 분야를 포함한 각분야에 일상적으로 쓰이게 될 것이다.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.439-442
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• 1990

A powerful general purpose image processing processor is developed using a high-speed DSP chip, TMS320C30. The image processing processor, compatible to the standard VME bus, is composed of VME bus interface unit, video rate image grabbing/coding unit, TMS320C30 interface unit and bank of high-speed SRAMs. The performance is evaluated experimentally with the general image processing algorithms and the results show that the developed processor is capable of high speed image processing.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05b
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• pp.1015-1018
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• 2003

본 논문은 날로 증가하는 데이터 처리 요구를 데이터 처리 전용 칩을 이용하여 데이터베이스, 데이터 마이닝, 또는 전문가 시스템 통과 같이 데이터 비교연산에 시간을 많이 소모하는 응용 소프트웨어의 처리 속도를 최소화 할 수 있는 시스템을 제안한다. 본 시스템은 기존의 숫자처리(numeric processing)보다는 기호처리(symbolic processing)를 위해서 관계 연산(relation operation) 모듈을 이용하여 입력된 데이터들을 하드웨어 레벨에서 고속으로 처리한다. 본 시스템은 칩으로 설계되어 하드디스크 레벨에서 시스템을 가속 시린 수도 있고, IP(Intellectual Property)로 구현되어 SoC(System-on-a-chip)의 한 모듈로서 프로세서 레벨에서 시스템을 가속시킬 수도 있다.

• Journal of information and communication convergence engineering
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• v.1 no.1
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• pp.48-52
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• 2003

A cost efficient IPSec Accelerator board utilizing a crypto chip and an entry-level Linux PC for the high performance VPN is presented in this paper. The IPIP (IP-over-IP tunneling) processing, encryption & decryption processing, HASH processing, and the integrity test functions of IPSec are processed in the IPSec Accelerator board. The proposed IPSec Accelerator has demonstrated successful execution of the required functions of the IPSec packet processing and verified its performance by processing the IPSec packets at the rate of over 1 Gbps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.33-44
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• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.

• Journal of Sensor Science and Technology
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• v.11 no.2
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• pp.84-92
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• 2002

A $32{\times}32$ pixels foveated (linear-polar) structure retina chip with the function of local-light adaptation for edge detection has been designed and fabricated using CMOS technology. Human retina can detect a wide range of light intensity. In this study, we use the biologically-inspired visual signal processing mechanism that consists of photoreceptors, horizontal cells, and bipolar cells in order to implement the function of edge detection in the retina chip. For a local-light adaptive function, the size of receptive field is changed locally according to the input light intensity. The spatial distribution of sensing pixels in the foveated retina chip has the advantages of selective reduction of image data and good resolution in central part to carry out the elaborate image processing with still enough resolution in the outer parts. The designed chip has been fabricated using standard $0.6\;{\mu}m$ double-poly triple-metal CMOS technology and optimized using HSPICE simulator.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.1
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• pp.18-25
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• 2018

In this paper, we present a low-power implementation of the multi-channel hearing aid system using a general-purpose DSP chip. The system includes an acoustic amplification algorithm based on Wide Dynamic Range Compression (WDRC), an adaptive howling canceller, and a single-channel noise reduction algorithm. To achieve a low-power implementation, each algorithm is re-constructed in forms of integer program, and the integer program is converted to the assembly program using BelaSigna(R) 250 instructions. Through experiments using the implementation system, the performance of each processing algorithm was confirmed in real-time. Also, the clock of the implementation system was measured, and it was confirmed that the entire signal processing blocks can be performed in real time at about 7.02MHz system clock.