• Journal of the Korean Ceramic Society
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• v.28 no.9
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• pp.675-682
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• 1991

Among many problems that need to be solved in the process of preparing multilayer chip LC filters, we studied the control of shrinkage in order to prevent the crack, warpage, and/or delamination which occurs at the interface between the inductance (L part) and the capacitance (C part). Shrinkage was controlled by compositions, powder size, calcining temperature and amount of organic binder. Capacitance sheet was prepared by mixing 65 wt% binder with the composition of 96 wt% TiO2 having an average particle size of 0.5 $\mu\textrm{m}$, 3 wt% CuO. After small amount of MnO2 and SiO2 added, it was calcined at 750$^{\circ}C$ for 2 hr. Inductance sheet was prepared by mixing 60 wt% binder with the composition of 49.5% mol% Fe2O3, 20.5 mol% ZnO, 20 mol% NiO and 10 mol% CuO which was calcined at 775$^{\circ}C$ for 2 hr. These sheets was laminated at 250 kg/$\textrm{cm}^2$, and cofired at 900$^{\circ}C$ for 2 hr to give rise to a multilayer chip LC filter without any warpage.

• Journal of Welding and Joining
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• v.31 no.3
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• pp.84-88
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• 2013

These days embedded technology may be the most significant development in the electronics industry. The study focused on the development of active device embedding using flexible printed circuit in view of process and materials. The authors fabricated 30um thickness Si chip without any crack, chipping defects with a dicing before grinding process. In order to embed chips into flexible PCB, the chip pads on a chip are connected to bonding pad on flexible PCB using an ACF film. After packaging, all sample were tested by the O/S test and carried out the reliability test. All samples passed environmental reliability test. In the future, this technology will be applied to the wearable electronics and flexible display in the variety of electronics product.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.65-71
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• 2022

In the case of Mobile PKG Trend is in a situation where a decrease in Mold Top Margin is inevitable due to its miniaturization and high capacity product requirements. However, conventional laser marking technology has an average depth of deep, and when applied to narrow top margin products, PKG strength is expected to decrease due to overlapping processing, and reliability is reduced due to poor quality such as chip damage due to laser exposure. Therefore, we have secured the technology through research on low-depth laser marking solutions that can accommodate narrow top margin products. As a result of the evaluation of applicable technology application for PKG development products, it was verified that the marking depth decreased by 67% reduced and the PKG strength increased by 12%. Furthermore, the quality verification of Laser Damage that can occur through PKG Mechanical analysis was performed, and no Chip Damage defects were found. This ensured the stability of mass production application quality.

• Journal of the Korean Society for Nondestructive Testing
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• v.12 no.4
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• pp.18-25
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• 1993

This paper is to aim the microdefect evaluation of If package into a quantitative from NDI's image processing of ultrasonic wave. (1) Automatically repeated discrimination analysis method can be devided in the category of all kind of defects on IC package, and also can be possible to have a sampling of partial delamination. (2) It is possible that the information of edge section in silicon chip surrounding can be extractor by the partial image processing of IC package. Also, the crack detection is possible between the resin part and lead frame.

• Journal of the Korean Society for Nondestructive Testing
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• v.10 no.2
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• pp.43-49
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• 1990

Ultrasonic testing is one of the most useful NDT method for detection of microdefect in the opaque materials. Recently, many applications of the ultrasonic techniques have been extended widely in the new field like electron is and advanced materials. From the result of the experiment, we have hardly found out a crack in the internal parts of the resin and a delamination between chip and resin because of poor performance of the system.

• Journal of the Korea Society of Computer and Information
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• v.8 no.4
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• pp.75-80
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• 2003

In this paper, we designed add current scan system basically. Although NDT system using AC method in now days had problem with limit of detection rate and limit of device organization, in this paper, we made up these problem so that designed device smaller than system used, reduction of cost of system organization and precision of measuring crack. Also, AC leakage flux system had high accuracy about minute crack in the surface and advantage of designing system easily so that we designed system for concerning about crack of surface. Furthermore, it can be able to detect exact crack of reference in wide area by using DSP320C31 chip to reduce the time of measuring crack.

• Electrical & Electronic Materials
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• v.10 no.6
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• pp.519-527
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• 1997

The micro crack was occurred where the stress concentrated by the thermal stress which was induced during the cooling period after molding process or by the various reliability tests. In order to estimate the possibility of development from inside micro crack to outside fracture, the fracture toughness of EMC should be measured under the various applicable condition. But study was conducted very rarely for the above area. In order to provide a was to decide the fracture resistance of EMC (Epoxy Molding Compound) of plastic package which is produced by using transfer molding method, measuring fracture is studied. The specimens were made with various EMC material. The diverse combination of test conditions, such as different temperature, temperature /humidity conditions, different filler shapes, and post cure treatment, were tried to examine the effects of environmental condition on the fracture toughness. This study proposed a way which could improve the reliability of LOC(Lead On Chip) type package by comparing the measured $J_{IC}$ of EMC and the calculated J-integral value from FEM(Finite Element Method). The measured $K_{IC}$ value of EMC above glass transition temperature dropped sharply as the temperature increased. The $K_{IC}$ was observed to be higher before the post cure treatment than after the post cure treatment. The change of $J_{IC}$ was significant by time change. J-integral was calculated to have maximum value the angle of the direction of fracture at the lead tip was 0 degree in SOJ package and -30 degree in TSOP package. The results FEM simulation were well agreed with the results of measurement within 5% tolerance. The package crack was proved to be affected more by the structure than by the composing material of package. The structure and the composing material are the variables to reduce the package crack.ack.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.12
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• pp.261-267
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• 2020

The demand for faster, lighter, and thinner portable electronic devices has brought about a change in semiconductor packaging technology. In response, a stacked chip-scale package(SCSP) is used widely in the assembly industry. One of the key materials for SCSP is a die-attach film (DAF). Excellent flowability is needed for DAF for successful die attachment without voids. For DAF with high flowability, two-step curing is often required to reduce a cure crack, but one-step curing is needed to reduce the processing time. In this study, DAF composition was categorized into three groups: cure (epoxy resins), soft (rubbers), hard (phenoxy resin, silica) component. The effect of the composition on a cure crack was examined when one-step curing was applied. The die-attach void and flowability were also assessed. The cure crack decreased as the amount of hard components decreased. Die-attach voids also decreased as the amount of hard components decreased. Moreover, the decrease in cure component became important when the amount of hard component was small. The flowability was evaluated using high-temperature storage modulus and bleed-out. A decrease in the amount of hard components was critical for the low storage modulus at 100℃. An increase in cure component and a decrease in hard component were important for the high bleed-out at 120℃(BL-120).

• Journal of the Korean Society for Precision Engineering
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• v.6 no.2
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• pp.40-46
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• 1989

Recently, the researches on cutting the new material have been done for development of aerospace industrial engineering. Especially, titanium ally is well known as heat resisting, antiwear, anticorrosion and difficult-to-machine materials. Many studies on the analysis of shear angle have been done for improving productivity in cutting these materials. In case of titanium alloy, the saw-toothed type of chip which has wave surface of a triangular form, an eccentric from of a continuous type of chip that is produced in the cutting process, was checked. Nakayama supposed that a maximum shear strewss plane and the shear crack in the free surface made an angle of $45^{\circ}$ .deg. , but it's usually much larger than that. In this paper, the author analyzed the shear conditions of the cutting process in the quick-stopping device with the help SEM-photographs, and measured the hypotenuse angle directly in the photographs of the chips. In conclusion, the author tried to find the shear angle in the cutting process with the saw-toothed chip and compared it with the shear angles which can be calculated from the theories established by others. The results obtained are as follows. 1. In case of the saw-toothed chips, the equivalent cutting ratio can be calculated by using the chip thickness to two-thirds of ramp height. 2. The theory of Ernst-Merchant is not applicable to the titanium and its alloys which does not fractured in accordance with the theory of maximum shear stress. 3. When we cut the titanium alloys which produced the saw-toothed chips, the shear angle can be found with the theories of Rowe-Spick, P.K. Wright and the measurement of hypotenuse angle.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.31-36
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• 2002

The 2nd level solder joint reliability of 153 FC-BGA for high-speed SRAM (Static Random Access Memory) with the large chip on laminate substrate comparing to PBGA(Plastic Ball Grid Array) was studied in this paper. This work has been done to understand an influence as the mounting with single side or double sides, structure of package, properties of underfill, properties and thickness of substrate and size of solder ball on the thermal cycling test. It was confirmed that thickness of BT(bismaleimide tiazine) substrate increased from 0.95 mm to 1.20 mm and solder joint fatigue life improved about 30% in the underfill with the low young's modulus. And resistance against the solder ball crack became twice with an increase of the solder ball size from 0.76 mm to 0.89 mm in solder joints.