• Title/Summary/Keyword: chip bonding

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Chip Pin Parasitic Extraction by Using TDR and NA (TDR 및 NA를 이용한 Chip Pin Parasitic 추출)

  • 이현배;박홍준
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.899-902
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    • 2003
  • Chip Pin Parasitic은 실제 Chip Pad에서부터 Bonding Wire를 통한 Package Lead Frame까지를 의미한다. 여기서, Lead Frame 및 Bonding Wire에서 Inductance 및 작은 저항이 보이고, Chip Pad에서의 Capacitance, 그리고 Pad 부터 Ground까지의 Return Path에서 발생하는 저항이 보인다. 이들을 모두 합하면 L, R, C의 Series로 나타낼 수 있다. 본 논문에서는 이런 Chip Pin Parasitic을 추출 하기 위해서 TDR(Time Domain Reflectometer)과 NA(Network Analyzer)를 사용하였는데, TDR의 경우 PCB를 제작하여 Chip을 Board위에 붙인 후 Time Domain에서 측정 하였고 NA의 경우 Pico Probe를 이용하여 Chip pin에 직접 Probing해서 Smith Chart를 통하여 Extraction 값을 추출했다. 이 경우, NA를 이용한 측정이 좀 더 정확한 Parasitic 값을 추출할 수 있으리라 예상되겠지만, 실제로 Chip이 구동하기 위해서는 Board위에 있을 때의 상황도 고려해야 하기 때문에 TDR 추출 값과 NA 추출 값을 모두 비교하였다.

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A study on the brittle characteristics of fused silica header driven by piezoelectric actuator for laser assisted TC bonding (레이저 열-압착 본딩을 위한 압전 액추에이터로 구동되는 용융실리카 헤더의 취성특성에 관한 연구)

  • Lee, Dong-Won;Ha, Seok-Jae;Park, Jeong-Yeon;Yoon, Gil-Sang
    • Design & Manufacturing
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    • v.13 no.4
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    • pp.10-16
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    • 2019
  • Semiconductor chip is bonded to the substrate by melting solder bumps. In general, the chip bonding is applied by a Reflow process or a Thermo-Compression(TC) bonding process. In this paper, we introduce a Laser Assisted Thermo-Compression bonding (LATCB) process to improve the anxiety of the existing process(Reflow, TC bonding). In the LATCB process, the chip is bonded to the substrate by irradiating a laser with a uniform energy density in the same area as the chip to melt only the solder bumps and press the chip with a Transparent Compression Module (TCM). The TCM consists of a fused silica header for penetrating the laser and pressurizing the chip, and a piezoelectric actuator (P.A.) coupled to both ends of the header for micro displacement control of the header. In addition, TCM is a structure that can pressurize the chip and deliver it to the chip and solder bumps without losing the energy of the laser. Fused silica, which is brittle, is vulnerable to deformation, so the header may be damaged when an external force is applied for pressurization or a displacement differenced is caused by piezoelectric actuators at both ends. On the other hand, in order to avoid interference between the header and the adjacent chip when pressing the chip using the TCM, the header has a notch at the bottom, and breakage due to stress concentration of the notch is expected. In this study, the thickness and notch length that the header does not break when the external force (500 N) is applied to both ends of the header are optimized using structural analysis and Coulomb-Mohr failure theory. In addition, the maximum displacement difference of the P.A.s at both ends where no break occurred in the header was derived. As a result, the thickness of the header is 11 mm, and the maximum displacement difference between both ends is 8 um.

Effects of Hardeners on the Low-Temperature Snap Cure Behaviors of Epoxy Adhesives for Flip Chip Bonding (플립칩용 에폭시 접착제의 저온 속경화 거동에 미치는 경화제의 영향)

  • Choi, Won-Jung;Yoo, Se-Hoon;Lee, Hyo-Soo;Kim, Mok-Soon;Kim, Jun-Ki
    • Korean Journal of Materials Research
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    • v.22 no.9
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    • pp.454-458
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    • 2012
  • Various adhesive materials are used in flip chip packaging for electrical interconnection and structural reinforcement. In cases of COF(chip on film) packages, low temperature bonding adhesive is currently needed for the utilization of low thermal resistance substrate films, such as PEN(polyethylene naphthalate) and PET(polyethylene terephthalate). In this study, the effects of anhydride and dihydrazide hardeners on the low-temperature snap cure behavior of epoxy based non-conductive pastes(NCPs) were investigated to reduce flip chip bonding temperature. Dynamic DSC(differential scanning calorimetry) and isothermal DEA(dielectric analysis) results showed that the curing rate of MHHPA(hexahydro-4-methylphthalic anhydride) at $160^{\circ}C$ was faster than that of ADH(adipic dihydrazide) when considering the onset and peak curing temperatures. In a die shear test performed after flip chip bonding, however, ADH-containing formulations indicated faster trends in reaching saturated bond strength values due to the post curing effect. More enhanced HAST(highly accelerated stress test) reliability could be achieved in an assembly having a higher initial bond strength and, thus, MHHPA is considered to be a more effective hardener than ADH for low temperature snap cure NCPs.

A Study on Fluxless Solder Flip Chip Bonding Using Plasma & Ultrasonic Wave (플라즈마와 초음파를 이용한 무플럭스 솔데 플립칩 접합에 관한 연구)

  • 홍순민;강춘식;정재필
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2001.11a
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    • pp.138-140
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    • 2001
  • Fluxless flip chip bonding using plasma & ultrasonic wave was investigated in order to evaluate the effect of plasma & ultrasonic treatment on the bondability of the Sn-3.5wt%Ag solder bumped die to TSM-coated glass substrate. The $Ar+10%H_2plasma$ was effective in removing tin oxide on solder surface. The die shear strength of the plasma-treated Si-chip is higher than that of non-treated specimen but lower than that of specimen bonded with flux. The die shear strength with the bonding load at 25W ultrasonic power increased to 0.8N/bump for all bonding temperature but decreased above 1.0N/bump.

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A New Wire Bonding Technique for High Power Package Transistor (고출력 트랜지스터 패키지 설계를 위한 새로운 와이어 본딩 방식)

  • Lim, Jong-Sik;Oh, Seong-Min;Park, Chun-Seon;Lee, Yong-Ho;Ahn, Dal
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.4
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    • pp.653-659
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    • 2008
  • This paper describes the design of high power transistor packages using high power chip transistor dies, chip capacitors and a new wire bonding technique. Input impedance variation and output power performances according to wire inductance and resistance for internal matching are also discussed. A multi crossing type(MCT) wire bonding technique is proposed to replace the conventional stepping stone type(SST) wire bonding technique, and eventually to improve the output power performances of high power transistor packages. Using the proposed MCT wire bonding technique, it is possible to design high power transistor packages with highly improved output power compared to SST even the package size is kept to be the same.

Fabrication of Porous Cu Layers on Cu Pillars through Formation of Brass Layers and Selective Zn Etching, and Cu-to-Cu Flip-chip Bonding (황동층의 형성과 선택적 아연 에칭을 통한 구리 필라 상 다공성 구리층의 제조와 구리-구리 플립칩 접합)

  • Wan-Geun Lee;Kwang-Seong Choi;Yong-Sung Eom;Jong-Hyun Lee
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.4
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    • pp.98-104
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    • 2023
  • The feasibility of an efficient process proposed for Cu-Cu flip-chip bonding was evaluated by forming a porous Cu layer on Cu pillar and conducting thermo-compression sinter-bonding after the infiltration of a reducing agent. The porous Cu layers on Cu pillars were manufactured through a three-step process of Zn plating-heat treatment-Zn selective etching. The average thickness of the formed porous Cu layer was approximately 2.3 ㎛. The flip-chip bonding was accomplished after infiltrating reducing solvent into porous Cu layer and pre-heating, and the layers were finally conducted into sintered joints through thermo-compression. With reduction behavior of Cu oxides and suppression of additional oxidation by the solvent, the porous Cu layer densified to thickness of approximately 1.1 ㎛ during the thermo-compression, and the Cu-Cu flip-chip bonding was eventually completed. As a result, a shear strength of approximately 11.2 MPa could be achieved after the bonding for 5 min under a pressure of 10 MPa at 300 ℃ in air. Because that was a result of partial bonding by only about 50% of the pillars, it was anticipated that a shear strength of 20 MPa or more could easily be obtained if all the pillars were induced to bond through process optimization.

2D and 3D Topology Optimization with Target Frequency and Modes of Ultrasonic Horn for Flip-chip Bonding (플립칩 접합용 초음파 혼의 목표 주파수와 모드를 고려한 2차원 및 3차원 위상최적화 설계)

  • Ha, Chang Yong;Lee, Soo Il
    • Transactions of the Korean Society for Noise and Vibration Engineering
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    • v.23 no.1
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    • pp.84-91
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    • 2013
  • Ultrasonic flip-chip bonding needs a precise bonding tool which delivers ultrasonic energy into chip bumps effectively to use the selected resonance mode and frequency of the horn structure. The bonding tool is excited at the resonance frequency and the input and output ports should locate at the anti-nodal points of the resonance mode. In this study, we propose new design method with topology optimization for ultrasonic bonding tools. The SIMP(solid isotropic material with penalization) method is used to formulate topology optimization and OC(optimal criteria) algorithm is adopted for the update scheme. MAC(modal assurance criterion) tracking is used for the target frequency and mode. We fabricate two prototypes of ultrasonic tools which are based on 3D optimization models after reviewing 2D and 3D topology optimization results. The prototypes are satisfied with the ultrasonic frequency and vibration amplitude as the ultrasonic bonding tools.