• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.89-92
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• 2004

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). we investigated the performance of $WO_3$ CMP used silica slurry, ceria slurry, tungsten slurry. In this paper, the effects of addition oxidizer on the $WO_3$ CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.57-58
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• 2006

Chemical-mechanical planarization (CMP) of Cu has used currently in semiconductor process for multilevel metallization system. This process requires the application of a considerable down-pressure to the sample in the polishing, because porous low-k films used in the Cu-multilevel interconnects of 65nm technology node are often damaged by mechanical process. Also, it make possible to reduce scratches and contaminations of wafer. Electrochemical mechanical planarization (ECMP) is an emerging extension of CMP. In this study, the electrochemical mechanical polisher was manufactured. And the static and dynamic potentiodynamic curve of Cu were measured in KOH based electrolyte and then the suitable potential was found.

• 한국빅데이터학회지
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• 제4권2호
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• pp.61-71
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• 2019

반도체 웨이퍼의 표면을 연마하여 평탄화하는 Chemical Mechanical Planarization(CMP) 공정은 다양한 화학물질과 물리적인 기계장치에 의한 작용을 받기 때문에 공정을 안정적으로 관리하기 힘들다. CMP 공정에서 품질 지표로는 Material Removal Rate(MRR)를 많이 사용하고, CMP 공정의 안정적 관리를 위해서는 MRR을 예측하는 것이 중요하다. 본 연구에서는 머신러닝 기법들을 이용하여 CMP 공정에서 수집된 시계열 센서 데이터를 분석하여 MRR을 예측하는 모형과 공정 품질을 해석하기 위한 분류 모형을 개발한다. 나아가 분류 결과를 분석하여, CMP 공정 품질에 영향을 미치는 유의미한 변수를 파악하고 고품질을 유지하기 위한 공정 조건을 설명한다.

• 전자공학회논문지D
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• 제34D권12호
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• pp.76-82
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• 1997

Chemical mechanical polishing (CMP) has become widely accepted for the planarization of multi-interconnect structures in semiconductor manufacturing. However, perfect planarization is not so easily ahieved because it depends on the pattern sensitivity, the large number of controllable process parameters, and the absence of a reliable process model, etc. In this paper, we realized the planarization of deposited oxide layers followed by metal (W) polishing as a replacement for tungsten etch-back process for via formation. Atomic force microscope (AFM) is used for the evaluation of pattern topography during CMP. As a result, AFM evaluation is very attractive compared to conventional methods for the measurment of planarity. mOreover, it will contribute to analyze planarization characteristics and establish CMP model.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.161-161
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• 2008

The oxide film of silicon wafer has been mainly polished by fumed silica, colloidal silica or ceria slurry. Because colloidal silica slurry is uniform and highly dispersed composed of spherical shape particles, by which the oxide film polished remains to be less scratched in finishing polishing process. Even though the uniformity and spherical shape is advantage for reducing the scratch, it may also be the factor to decrease the removal rate. We have studied the correlation of silica abrasive particles and CMP characteristics by varying pH, down force, and table rotation rate in polishing. It was found that the CMP polishing is dependent on the morphology, aggregation, and the surface property of the silica particles.

• Transactions on Electrical and Electronic Materials
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• 제3권4호
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• pp.5-9
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• 2002

Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. Especially, to achieve the higher density and greater performance, shallow trench isolation (STI)-CMP process has been attracted attention for multilevel interconnection as an essential isolation technology. Also, it was possible to apply the direct STI-CMP process without reverse moat etch step using high selectivity slurry (HSS). In this work, we determined the process margin with optimized process conditions to apply HSS STI-CMP process. Then, we evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions. The wafer-to-wafer thickness variation and day-by-day reproducibility of STI-CMP process after repeatable tests were investigated. Our experimental results show, quite acceptable and reproducible CMP results with a wafer-to-wafer thickness variation within 400$\AA$.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.207-210
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• 2003

The chemical mechanical planarization (CMP) process is a method of planarizing semiconductor wafers with a high degree of success. However, fundamental mechanisms of the process are not fully understood. Several theoretical analyses have been introduced, which are focused on kinematics, von Mises stress distributions and hydrodynamic lubrication aspects. This paper is concerned with hydrodynamic lubrication theory as the chemical mechanical planarization model; the three-dimensional Reynolds equation is applied to predict slurry film thickness and pressure distributions between the pad and the wafer. This paper classifies geometry of wafer into 3 types and focuses on the differences between them.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 추계학술대회 논문요약집
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• pp.56-56
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• 2003

• 한국전기전자재료학회논문지
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• 제16권6호
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• pp.465-470
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• 2003

The chemical mechanical polishing (CMP) process has been widely used for the global planarization of multi-layer structures in semiconductor manufacturing. The CMP process can be optimized by several parameters such as equipment, consumables (pad, backing film and slurry), process variables and post-CMP cleaning. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, the slurry dominates more than 40 %. In this paper, we have studied the CMP characteristics of diluted silica slurry by adding of raw alumina abrasives and annealed alumina abrasives. As an experimental result, we obtained the comparable slurry characteristics compared with original silica slurry in the view-point of high removal rate and low non-uniformity. Therefore, we can reduce the cost of consumables(COC) of CMP process for ULSI applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.149-153
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• 2003

Chemical mechanical polishing (CMP) technology for global planarization of multi-level inter-connection structure has been widely studied for the next generation devices. CMP process has been paid attention to planarized pre-metal dielectric (PMD), inter-layer dielectric (ILD) interconnections. Expecially, shallow trench isolation (STI) used to CMP process on essential. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between $SiO_2$ and $Si_3N_4$ films for the purpose of process simplification and n-situ end point detection(EPD). However, STI-CMP process has various defects such as nitride residue, tom oxide and damage of silicon active region. To solve these problems, in this paper, we studied the planarization characteristics using a high selectivity slurry(HSS). As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of HSS STI-CMP process.