• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.453-456
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• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.13-16
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• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.6
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• pp.304-310
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• 2002

Novel charge trap type memory devices with reoxidized oxynitride gate dielectrics made by NO annealing and reoxidation process of initial oxide on substrate have been fabricated using 0.35 $\mu \textrm{m}$ retrograde twin well CMOS process. The feasibility for application as NVSM memory device and characteristics of traps have been investigated. For the fabrication of gate dielectric, initial oxide layer was grown by wet oxidation at $800^{\circ}C$ and it was reoxidized by wet oxidation at $800^{\circ}C$ after NO annealing to form the nitride layer for charge trap region for 30 minutes at $850^{\circ}C$. The programming conditions are possible in 11 V, 500 $\mu \textrm{s}$ for program and -13 V, 1ms for erase operation. The maximum memory window is 2.28 V. The retention is over 20 years in program state and about 28 hours in erase state, and the endurance is over $3 \times 10^3$P/E cycles. The lateral distributions of interface trap density and memory trap density have been determined by the single junction charge pumping technique. The maximum interface trap density and memory trap density are $4.5 \times 10^{10} \textrm{cm}^2$ and $3.7\times 10^{18}/\textrm{cm}^3$ respectively. After $10^3$ P/E cycles, interlace trap density increases to $2.3\times 10^{12} \textrm{cm}^2$ but memory charges decreases.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.914-920
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• 2000

When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.9-12
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• 1998

Film characteristics of thin reoxidized nitrided oxides were investigated by SIMS analysis and C-V method in order to use the gate dielectric for charge-trap type NVSMs instead of ONO stacked layers. Nitric oxide(NO) annealed film has the nitrogen content sharply peaked at the Si-SiO$_2$ interface, while it is broad for nitrous oxide($N_2$O) ambient. The nitrogen peak concentration increased with anneal temperature and time. The position of nitrogen content in the oxide layer was due to be precisely controlled. For the films annealed NO ambient at 80$0^{\circ}C$ for 30min. followed by reoxidized at 85$0^{\circ}C$, the maximum memory window of 3.5V was obtained and the program condition was +12V, 1msec for write and -l3V, 1msec for erase.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.37-40
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• 1999

For the first time, charge trapping nonvolatile semiconductor memories with the deoxidized oxynitride gate dielectric is proposed and demonstrated. Gate dielectric wit thickness of less than 1 nm have been grown by postnitridation of pregrown thermal silicon oxides in NO ambient and then reoxidation. The nitrogen distribution and chemical state due to NO anneal/reoxidation were investigated by M-SIMS, TOF-SIMS, AES depth profiles. When the NO anneal oxynitride film was reoxidized on the nitride film, the nitrogen at initial oxide interface not only moved toward initial oxide interface, but also diffused through the newly formed tunnel oxide by exchange for oxygen. The results of reoxidized oxynitride(ONO) film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/N-rich SiON interface/Si-rich SiON(nitrogen diffused tunnel oxide)/Si substrate. In addition, the SiON and the S1$_2$NO Phase is distributed mainly near the tunnel oxide, and SiN phase is distributed mainly at tunnel oxide/Si substrate interface.