• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1133-1138
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• 2018

Lightweight Encryption Algorithm (LEA) is one of the most promising lightweight block cipher algorithm due to its high efficiency and security level. There are many works on the efficient LEA implementation. However, many works missed the secure application services where the IoT platforms perform secure communications between heterogeneous IoT platforms. In order to establish the secure communication channel between them, the encryption should be performed in the on-the-fly method. In this paper, we present the LEA implementation performing the on-the-fly method over the ARM Cortex-M3 processors. The general purpose registers are fully utilized to retain the required variables for the key scheduling and encryption operations and the rotation operation is optimized away by using the barrel-shifter technique. Since the on-the-fly method does not store the round keys, the RAM requirements are minimized. The implementation is evaluated over the ARM Cortex-M3 processor and it only requires 34 cycles/byte.

• Journal of Positioning, Navigation, and Timing
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• v.7 no.2
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• pp.53-59
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• 2018

This paper proposes a pseudo-random beamforming technique for time-synchronized mobile base stations (BSs) for multi-cell downlink networks which have mobility. The base stations equipped with multi-antennas and mobile stations (MSs) are time-synchronized based on global positioning system (GPS) signals and generate a number of transmit beamforming matrix candidates according to the predetermined pseudo-random pattern. In addition, MSs generate receive beamforming vectors that correspond to the beam index number based on the minimum mean square error (MMSE) using transmit beamforming vectors that make up a number of transmit beamforming matrices and wireless channel matrices from BSs estimated via the reference signals (RS). Afterward, values of received signal-to-interference-plus-noise ratio (SINR) with regard to all transmit beamforming vectors are calculated, and the resulting values are then feedbacked to the BS of the same cells along with the beam index number. Each of the BSs calculates each of the sum-rates of the transmit beamforming matrix candidates based on the feedback information and then transmits the calculated results to the BS coordinator. After this, optimum transmit beamforming matrices, which can maximize a sum-rate of the entire cells, are selected at the BS coordinator and informed to the BSs. Finally, data signals are transmitted using them. The simulation results verified that a sum-rate of the entire cells was improved as the number of transmit beamforming matrix candidates increased. It was also found that if the received SINR values and beam index numbers are feedbacked opportunistically from each of the MSs to the BSs, not only nearly the same performance in sum-rate with that of applying existing feedback techniques could be achieved but also an amount of feedback was significantly reduced.

• Journal of the Korea Society of Computer and Information
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• v.15 no.5
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• pp.103-111
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• 2010

This paper proposes an efficient data transmission strategy using adaptive-tier low transmission power schedule in a TDMA-based ad hoc MAC protocol. Since the network resource of ad hoc networks has the characteristic of reassignment due to the multiple interferences and the contention-based limited wireless channel, the efficient time slot assignment and low power transmission scheme are the main research topics in developing ad hoc algorithms. Based on the proposed scheme of interference avoidance when neighbor clusters transmit packets, this paper can minimize the total energy dissipation and maximize the utilization of time slot in each ad hoc node. Simulation demonstrates that the proposed algorithm yields 15.8 % lower energy dissipation and 4.66% higher time slot utilization compared to the ones of two-tier conventional energy dissipation model.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.9
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• pp.3172-3193
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• 2022

Cognitive radio-simultaneous wireless information and power transfer (CR-SWIPT) has attracted much interest since it can improve both the spectrum and energy efficiency of wireless networks. This paper focuses on the resource sharing between a point-to-point primary system (PRS) and a multiuser multi-antenna cellular cognitive radio system (CRS) containing a large number of cognitive users (CUs). The resource sharing optimization problem is formulated by jointly scheduling CUs and adjusting the transmit power at the cognitive base station (CBS). The effect of accessing CUs' spatial channel correlation on the possible transmit power of the CBS is investigated. Accordingly, we provide a low-complexity suboptimal approach termed the semi-correlated semi-orthogonal user selection (SC-SOUS) algorithm to enhance the spectrum efficiency. In the proposed algorithm, CUs that are highly correlated to the information decoding primary receiver (IPR) and mutually near orthogonal are selected for simultaneous transmission to reduce the interference to the IPR and increase the sum rate of the CRS. We further develop a spatial correlation-based resource sharing (SC-RS) strategy to improve energy sharing performance. CUs nearly orthogonal to the energy harvesting primary receiver (EPR) are chosen as candidates for user selection. Therefore, the EPR can harvest more energy from the CBS so that the energy utilization of the network can improve. Besides, zero-forcing precoding and power control are adopted to eliminate interference within the CRS and meet the transmit power constraints. Simulation results and analysis show that, compared with the existing CU selection methods, the proposed low-complex strategy can enhance both the achievable sum rate of the CRS and the energy sharing capability of the network.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.592-607
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• 2006

This paper proposes a technique to select processors and hardware IPs and to map the tasks into the selected processing elements, aming to achieve high performance with minimal system cost when multitask applications with real-time constraints are run on a multicore SoC. Such technique is called to 'Hardware-Software Cosynthesis Technique'. A cosynthesis technique was already presented in our early work [1] where we divide the complex cosynthesis problem into three subproblems and conquer each subproblem separately: selection of appropriate processing components, mapping and scheduling of function blocks to the selected processing component, and schedulability analysis. Despite good features, our previous technique has a serious limitation that a task monopolizes the entire system resource to get the minimum schedule length. But in general we may obtain higher performance in multitask multicore system if independent multiple tasks are running concurrently on different processor cores. In this paper, we present two mapping techniques, task mapping avoidance technique(TMA) and task mapping pinning technique(TMP), which are applicable for general cases with diverse operating policies in a multicore environment. We could obtain significant performance improvement for a multimedia real-time application, multi-channel Digital Video Recorder system and for randomly generated multitask graphs obtained from the related works.

• Journal of Broadcast Engineering
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• v.15 no.2
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• pp.205-216
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• 2010

In this paper, a method of MPEG-2 Transport Stream (TS) multiplexing for Ultra HDTV (UHDTV) and its design and implementation as a SW tool is described. In practice, UHD video may be divided into several HD videos and each video is encoded in parallel. Therefore, it is necessary to synchronize and multiplex multiple bitstreams encoding each HD video for transmitting and storing UHD video. In this paper, it is assumed that 4 HD videos partitioning a UHD spatially are encoded as H.264/AVC and two 5.0 channel audios are encoded by AC-3. Therefore, 4 H.264/AVC elementary streams (ESs) and 2 AC-3 ESs is mainly considered in the TS multiplexing of UHD. For the carriage of H.264/AVC and AC-3 over MPEG-2 TS, PES packetization and TS multiplexing are designed and implemented based on the extended specification of the MPEG-2 Systems and ATSC (Digital audio compressed standard), respectively. The implemented UHD TS multiplexing tool emulates real time HW operation in the time unit corresponding to the duration of one TS packet transmission in a given TS rate. In particular, in order to satisfy the timing model, the buffers defined in the TS System Target Decoder (T-STD) are monitored and their statuses are considered in the scheduling of TS multiplexing. For UHD multiplexing, two kinds of multiplexing structures, which are UHD re-multiplexing and UHD program multiplexing, are implemented and their strength and weakness are investigated. The developed UHD TS multiplexing tool is tested and verified in terms of the syntax and semantics conformance and functionalities by using a commercial analyzer and real-time presentation tools.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.