• 정보저장시스템학회논문집
• /
• 제1권2호
• /
• pp.155-160
• /
• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

• International Journal of Internet, Broadcasting and Communication
• /
• 제15권4호
• /
• pp.74-83
• /
• 2023

In this paper, we propose an image compression scheme which uses a demosaicking network and a channel-wise decoder in the decoding network. For the demosaicing network, we use as the input a colored mosaiced pattern rather than the well-known Bayer pattern. The use of a colored mosaiced pattern results in the mosaiced image containing a greater amount of information pertaining to the original image. Therefore, it contributes to result in a better color reconstruction. The channel-wise decoder is composed of multiple decoders where each decoder is responsible for each channel in the color image, i.e., the R, G, and B channels. The encoder and decoder are both implemented by wavelet based auto-encoders for better performance. Experimental results verify that the separated channel-wise decoders and the colored mosaic pattern produce a better reconstructed color image than a single decoder. When combining the colored CFA with the multi-decoder, the PSNR metric exhibits an increase of over 2dB for three-times compression and approximately 0.6dB for twelve-times compression compared to the Bayer CFA with a single decoder. Therefore, the compression rate is also increased with the proposed method than with the method using a single decoder on the Bayer patterned mosaic image.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 하계종합학술대회 논문집
• /
• pp.825-828
• /
• 1999

A Viterbi Decoder for IMT2000 Mobile Station based on cdma200 is implemented in this paper. There are fundamental traffic channel, supplemental traffic channel for user data transmission and dedicated control channel for signal transmission in cdma2000. This decoder can decode these channels simultaneously, and support l/2, l/3, 1/4 code rate decoding. In case of fundamental channel decoding, it needs about 1100 logic cells and 30000 bit memory block.

• 대한전자공학회논문지
• /
• 제15권3호
• /
• pp.11-17
• /
• 1978

Medium scale 집적회로인 BCD to seven segment decoder/driver를 P-channel Metal-Oxide-Semiconductor집적회로 제작 기법으로 설계, 제작하였다. 본 소자는 특별히 common cathode seven segment light emitting diode에 적합하도록 설계되었다. decoder logic은 직렬로 연결된 두 개의 Read-Only-Memory로 구성되어 있으며 driver로는 channel이 넓은 FET를 사용하였다. 제작된 집적회로는 전원 전압이 -7 volt에서 -26 volt까지 변화할 때 정상적으로 동작하였으며 LED각 segment 전류의 non-uniformity는 약 ±10%이었다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
• /
• pp.295-298
• /
• 2003

In this paper, a novel maximum a posterion (MAP) estimation for the channel decoding of H.264 codes in the presence of transmission error is presented. Arithmetic codes with a forbidden symbol and trellis search techniques are employed in order to estimate the best transmitted. And, there has been growing interest of communication, the research about transmission of exact data is increasing. Unlike the case of voice transmission, noise has a fatal effect on the image transmission. The reason is that video coding standards have used the variable length coding. So, only one bit error affects the all video data compressed before resynchronization. For reasons of that, channel needs the channel codec, which is robust to channel error. But, usual channel decoder corrects the error only by channel error probability. So, designing source codec and channel codec, Instead of separating them, it is tried to combine them jointly. And many researches used the information of source redundancy In received data. But, these methods do not match to the video coding standards, because video ceding standards use not only one symbol but also many symbols in same data sequence. In this thesis, We try to design combined source-channel codec that is compatible with video coding standards. This MAP decoder is proposed by adding semantic structure and semantic constraint of video coding standards to the method using redundancy of the MAP decoders proposed previously. Then, We get the better performance than usual channel coder's.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2005년도 추계종합학술대회
• /
• pp.423-426
• /
• 2005

In this paper, we propose a receiver that combines a channel detector with a channel decoder to retrieve information from ISI and AWGN in an iteratively manner. The receiver, evolving from a system of a PRML detector and a RS decoder, consists of a SOVA detector followed by a LDPC decoder and has them exchange information iteratively. Rather than handling extrinsic reliabilities explicitly as in Turbo equalization, we take hard-decision values from the LDPC decoder and mix them with the channel output in a certain ratio as input for SOVA. The scheme, simply modified to the one-way structure of a SOVA and a LDPC decoder, shows improved performance with iteration numbers as well as the combining ratio of the channel output and the feedback output. We additionally analyze the receiver with a simple theoretical model and present some valuable properties.

• 디지털산업정보학회논문지
• /
• 제14권4호
• /
• pp.79-85
• /
• 2018

This paper presents an implementation method of Long Term Evolution-Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a general-purpose multicore Digital Signal Processor (DSP), TMS320C6670. Although the DSP provides some useful coprocessors such as turbo decoder, fast Fourier transformer, Viterbi Coprocessor, Bit Rate Coprocessor etc., it is specific to the base station platform implementation not the mobile terminal platform implementation. This paper shows an implementation method of the LTE-A PDSCH decoder using programmable DSP cores as well as the coprocessors of Fast Fourier Transformer and turbo decoder. First, it uses the coprocessor supported by the TMS320C6670, which can be used for PDSCH implementation. Second, we propose a core programming method using DSP optimization method for block diagram of PDSCH that can not use coprocessor. Through the implementation, we have verified a real-time decoding feasibility for the LTE-A downlink physical channel using test vectors which have been generated from LTE-A Reference Measurement Channel (RMC) Waveform R.6.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권5호
• /
• pp.465-472
• /
• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2008년도 제39회 하계학술대회
• /
• pp.1939-1940
• /
• 2008

1967년 Andrew J. Viterbi에 의해 처음 제안된 Viterbi 알고리즘은 길쌈부호(convolution code)의 대표적인 복호방법으로 현재 통신 기술 중에서 가장 많이 쓰이는 것 중에 하나이다. Viterbi decoder는 사용되는 시스템의 사양에 따라 에러 수정 능력이 다른데 통신 channel 상의 오류뿐만 아니라 Viterbi decoder내부에 있는 메모리에서 발생하는 오류도 Viterbi decoder의 에러 수정 능력에 영향을 준다. 본 논문에서는 일반적으로 많이 확인되었던 channel상의 오류와 함께 Viterbi decoder내부에 있는 메모리에서 오류가 발생했을 때 복.부호기의 사양에 따른 에러정정능력을 분석하였다.

• 한국통신학회논문지
• /
• 제29권4C호
• /
• pp.448-453
• /
• 2004

기존의 QPSK와 TC-8PSK 신호를 복호할 수 있는 pragmatic TCM은 3bit 연판정을 적용한 Viterbi 복호기를 이용하기 위해서 sector phase quantizer가 필요하다. 이러한 단점을 보완하기 위해서 sector phase quantizer가 필요치 않고서 간단히 심볼 변환을 이용하여 연판정 출력이 가능한 새로운 알고리즘을 제안해서 이에 구조 및 성능을 분석하였으며 아울러 터보 부호에도 적용하였다. 성능 분석 결과, 기존의 pragmatic TCM에 비해 Euclidean 거리의 증가로 약 1［㏈］의 성능 향상을 가져옴을 알 수 있다.