• Journal of IKEEE
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• 제2권2호
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제21권11호
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• pp.1275-1284
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• 2010

100 MHz bandwidth and 1 Gbit/s data speed are needed in LTE-advanced for the next generation mobile communication system. Therefore, spectrum aggregation method has been studied recently to extend usable frequency bands. Also bandwidth utilization is increased since vacant frequencies are used to communicate. However, transceiver structure requires the digital RF and SDR. Therefore, frequency synthesizer and PA must operate over wide-bandwidth and RF impairments also increases in transceiver. Uplink of LTE advanced uses DFT-S OFDM using plural power amplifier. The effect of ICI increases in frequency domain of receiver due to phase noise and IQ imbalance. In this paper, we analyze influences of ICI in frequency domain of receiver considering phase noise and IQ imbalance in multiband system. Also, we separate phase noise and IQ imbalance effect from channel response in frequency domain of uplink system. And we propose a method to estimate the channel exactly and to compensate IQ imbalance and phase noise. Simulation result shows that the proposed method achieves the 2 dB performance gain of BER=$10^{-4}$.

• Applied Biological Chemistry
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• 제47권3호
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• pp.300-306
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• 2004

Eight cation or anion-responsive polymer membranes were prepared by a casting procedure employing polyvinyl chloride, Bis (2-ethylhexyl)sebacate and each electroactive material in the ratio of 66 : 33 : 1. The resulting membranes were separately installed onto the sensitive area of the ionic electrodes to produce an 8-channel taste sensor array. The taste sensors of the array were connected to a high-input impedance amplifier and the amplified sensor signals were interfaced to a PC via an A/D converter. The taste evaluation system was applied to a discriminant analysis on six groups of marketed beverages like sikhye, sujunggwa, tangerine juice, ume juice, ionic drink and green tea. When the signal data from the sensor array were analyzed by principal component analysis after normalization, the 1st, 2nd and 3rd principal component explained most of the total data variance. The six groups of the analyzed beverages were discriminated well in the three dimensional principal component space. The half of the five groups of the analyzed beverages was also discriminated in the two dimensional principal component plane.

• Journal of the Institute of Electronics and Information Engineers
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• 제53권3호
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제39A권5호
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• pp.258-270
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• 2014

In this paper, we investigate channel capacity of two kinds of uplink OFDMA (Orthogonal Frequency Division Multiple Access) schemes, i.e. ZCZ (Zero Correlation Zone) code time-spread OFDMA and sparse SC-FDMA (Single Carrier Frequency Division Mmultiple Access) robust to access timing offset (TO) among multiple users. In order to reflect the practical condition, we consider not only access TO among multiple users but also peak to average power ratio (PAPR) which is one of hot issues of uplink OFDMA. In the case with access TO among multiple users, the amplified signal of users by power control might affect a severe interference to signals of other users. Meanwhile, amplified signal by considering distance between user and base station might be distorted due to the limit of amplifier and thus the performance might degrade. In order to achieve the maximum channel capacity, we investigate the combinations of transmit power so called ASF (adaptive scaling factor) by numerical simulations. We check that the channel capacity of the case with ASF increases compared to the case with considering only distance i.e. ASF=1. From the simulation results, In the case of high signal to noise ratio (SNR), ZCZ code time-spread OFDMA achieves higher channel capacity compared to sparse block SC-FDMA. On the other hand, in the case of low SNR, the sparse block SC-FDMA achieves better performance compared to ZCZ time-spread OFDMA.

• Journal of IKEEE
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• 제25권1호
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• pp.156-167
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• 2021

In this paper, we propose a digital transceiver unit design for in-building of 5G optical repeaters that extends the coverage of 5G mobile communication network services and connects to a stable wireless network in a building. The digital transceiver unit for driving the proposed 5G optical repeater is composed of 4 blocks: a signal processing unit, an RF transceiver unit, an optical input/output unit, and a clock generation unit. The signal processing unit plays an important role, such as a combination of a basic operation of the CPRI interface, a 4-channel antenna signal, and response to external control commands. It also transmits and receives high-quality IQ data through the JESD204B interface. CFR and DPD blocks operate to protect the power amplifier. The RF transmitter/receiver converts the RF signal received from the antenna to AD, is transmitted to the signal processing unit through the JESD204B interface, and DA converts the digital signal transmitted from the signal processing unit to the JESD204B interface and transmits the RF signal to the antenna. The optical input/output unit converts an electric signal into an optical signal and transmits it, and converts the optical signal into an electric signal and receives it. The clock generator suppresses jitter of the synchronous clock supplied from the CPRI interface of the optical input/output unit, and supplies a stable synchronous clock to the signal processing unit and the RF transceiver. Before CPRI connection, a local clock is supplied to operate in a CPRI connection ready state. XCZU9CG-2FFVC900I of Xilinx's MPSoC series was used to evaluate the accuracy of the digital transceiver unit for driving the 5G optical repeater proposed in this paper, and Vivado 2018.3 was used as the design tool. The 5G optical repeater digital transceiver unit proposed in this paper converts the 5G RF signal input to the ADC into digital and transmits it to the JIG through CPRI and outputs the downlink data signal received from the JIG through the CPRI to the DAC. And evaluated the performance. The experimental results showed that flatness, Return Loss, Channel Power, ACLR, EVM, Frequency Error, etc. exceeded the target set value.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제43권12호
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Progress in Medical Physics
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• 제19권4호
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• pp.285-290
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• 2008

In this study, we have fabricated a one-dimensional fiber-optic dosimeter for electron beam therapy dosimetry. Each fiber-optic dosimeter has an organic scintillator with a plastic optical fiber and it is embedded and arrayed in the plastic phantom to measure one-dimensional high energy electron beam profile of clinical linear accelerator. The scintillating lights generated from each sensor probe are guided by plastic optical fibers to the multi-channel photodiode amplifier system. We have measured one-dimensional electron beam profiles in a PMMA phantom according to different field sizes and energies of electron beam. Also, the isodose and three-dimensional percent depth dose curves in a PMMA phantom are obtained using a one-dimensional fiber-optic dosimeter with different electron beam energies.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제35권8A호
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• pp.777-784
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• 2010

Recently, the necessity of underwater communication and demand for transmitting and receiving various data such as voice or high resolution image data are increasing as well. The performance of underwater acoustic communication system is influenced by characteristics of the underwater communication channels. Especially, ISI(inter symbol interference) occurs because of delay spread according to multi-path and communication performance is degraded. In this paper, we study the OFDM technique to overcome the delay spread in underwater channel and by using CP, we compensate for delay spread. But PAPR which OFDM system has problem is very high. Therefore, we use DFT-spread OFDM method to avoid nonlinear distortion by high PAPR and to improve efficiency of amplifier. DFT-spread OFDM technique obtains high PAPR reduction effect because of each parallel data loads to all subcarrier by DFT spread processing before IFFT. In this paper, we show performance about delay spread through OFDM system and verify method that DFT spread OFDM is more suitable than OFDM for underwater communication. And we analyze performance according to two subcarrier mapping methods(Interleaved, Localized). Through the simulation results, performance of DFT spread OFDM is better about 5~6dB at $10^{-4}$ than OFDM. When compared to BER according to subcarrier mapping, Interleaved method is better about 3.5dB at $10^{-4}$ than Localized method.

• Journal of the Institute of Electronics and Information Engineers
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• 제49권12호
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.