• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.9
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• pp.2154-2172
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• 2013

A centralized cognitive radio (CR) network is proposed and its system capacity is studied. The CR network is designed with power control and multi-user scheduling schemes to support best-effort traffics under peak interference power constraints. We provide an analytical framework to quantify its system capacity, taking into account various key factors such as interference constraints, density of primary users, cell radius, the number of CR users, and propagations effects. Furthermore, closed-form formulas are derived for its capacities when only path loss is considered in the channel model. Semi-analytical expressions for the capacities are also given when more realistic channel models that include path loss, shadowing, and small-scale fading are used. The accuracy of the proposed analytical framework is validated by Monte Carlo simulations. Illustrated with a practical example, the provided analytical framework is shown to be useful for the strategic planning of centralized CR networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.423-428
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• 2008

We consider the use of cooperative diversity in a multiuser wireless data network. This paper provides an analysis of the interaction between cooperative diversity and multiuser diversity on downlink channels. By using approximation of the signal-to-noise ratio (SNR) distribution of each cooperative diversity link by Gamma distribution, an analytic expression is derived for the average throughput of a single-cell wireless system with multiple cooperative diversity links combined with a fair-access scheduler. The proposed analytic approach is verified through comparisons with simulated results and shows that cooperative diversity makes the detrimental impacts on multiuser diversity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.1907-1914
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• 1998

This paper proposes the adaptive connection admission cotrol using the variale MRR(measurement reflection ratio) and the distribution of the number of cells arriving during the fixed interval. This distribution is estimated from the measured number of cells arriving at the output buffer during the fixed interval and traffic parameters specified by user. MRR is varied by the difference of estimated distribution and measurement distribution. As MRR is adaptively varied by estimated distribution error of accepted connections, it quickly reduces estimation error. Also, the scheduling scheme is proposed for multiplexed traffic with various traffic characteristics. For each traffic class, this scheme estimates adaptively equivalent bandwidth and schedules according to equivalent bandwidth ratio of each traffic class, so it improves cell loss rate and link utilization.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.181-189
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• 2001

In this thesis, a policing algorithm is proposed, which is one of the traffic management function in ATM networks. The proposed algorithm minimizes CLR(Cell Loss patio) of high priority cells and solves burstiness problem of the traffic caused by multiplexing and demultiplexing process. The proposed algorithm has been implemented with VHDL and is divided into three parts, which are an input module, an UPC module, and an output module. In implementation of the UPC module\`s memory access, memory address is assigned according to VCI\`s LSB(Lowest Significant Byte) of ATM header for convenience. And the error of VSA operation from counter\`s wrap-around can be recovered by the proposed method. ANAM library 0.25 $\mu\textrm{m}$ and design compiler of Synopsys are used for synthesis of the algorithm and Synopsys VSS tool is used for VHDL simulation of it

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2382-2388
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• 2014

To provide network reliability in indoor wireless communication systems, we should resolve the problem of unexpected network failure rapidly. In this paper, we propose an adaptive resource management (ARM) scheme to support seamless connectivity to users. In consideration of system throughput and user fairness simultaneously, the ARM scheme adaptively determines the set of healing channels, and performs scheduling and power allocation iteratively based on a constrained non-convex optimization technique. Through intensive simulations, we demonstrate the superior performance results of the proposed ARM scheme in terms of the average cell capacity and user fairness.

• Journal of KIISE:Information Networking
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• v.27 no.3
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• pp.331-338
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• 2000

온라인 화상회의, VOD 등의 멀티캐스트(multicast)특성을 갖는 서비스를 효율적으로 제공하기 위해서는 스위치 수준에서의 멀티캐스트 트래픽 처리를 위한 연구가 필요하다. ATM 스위치 증 입력 버퍼형은 하드웨어 구현 복잡도가 낮아 고속의 트래픽 처리와 대용량 스위치 구현에 적합한 반면, 높은 성능을 가지기 위해서는 임의접근(random access) 입력버퍼와 좋은 셀 스케쥴링 알고리즘이 필요하다. 본 논문에서는 입혁버퍼형 ATM 스위치에서의 멀티캐스트 셀 스케쥴링 알고리즘인 무충동 시간예약(CFTR)기법을 제안한다. CFTR 기법은 입력버퍼의 셀의 전송시점을 충돌이 없도록 예약함으로써 높은 처리율을 가질 수 있도록 하며, 이를 위해 입력단, 출력단 스케쥴러에 예약 테이블을 둔다. CFTR 기법은 각 출력 단 스케쥴러에서의 예약과정이 간단하고 독립적, 병렬적 수행이 가능하므로 고속 트래픽 처리에 적합하다. CFTR 기법의 성능평가를 위해 시뮬레이션을 통해 기존의 셀 스케쥴링 방식과 비교하며, 약간의 하드웨어 추가로 매우 좋은 성능을 보임을 알 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.63-72
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• 2012

In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.427-433
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• 2002

This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.157-165
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• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• Korean Journal of Construction Engineering and Management
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• v.12 no.6
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• pp.31-41
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• 2011

Since the cases of time extension have continuously transpired in the public construction project, the potential of economical loss and claims is increasing because the concerned parties such as an owner or a contractor have not properly performed their own responsibility for time extension. One of the main reasons is that the present planning and scheduling do not support the method to apportion the proper responsibility to the right party. This problem has repeatedly led to time extension and made it difficult for the concerned parties to perform the responsibility for time extension. In order to overcome this problem, a framework of delay administration is required as the method to apportion the proper responsibility to the right party. To solve this problem, this paper aimed to develop the conceptual model and prototype system as the practical method to administrate delay causation. Furthermore, the verification result for the reliability and applicability throughout the case studies on real construction projects shows that the conceptual model and prototype system developed would help efficiently to administrate the delay causation.