• The Plant Pathology Journal
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• v.23 no.4
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• pp.281-286
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• 2007

Interactions between viral proteins and host proteins are essential for virus replication. Especially, translation of viral genes completely depends on the host machinery. In potyviruses, interactions of genome-linked viral protein (VPg) with host translation factors including eIF4E, eIF(iso)4E, and poly(A)-binding protein (PABP) has previously been characterized. In this study, we investigated interactions between Soybean mosaic virus (SMV) viral proteins and host translation factors by yeast two-hybrid system. SMV VPg interacted with eIF4E, eIF(iso)4E, and PABP in yeast two-hybrid system, while SMV helper component proteinase (HC-pro) interacted with neither of those proteins. The interaction between SMV NIb and PABP was also detected. These results are consistent with those reported previously in other potyviruses. Interestingly, we found reproducible and specific interactions between SMV coat protein (CP) and PABP. Deletion analysis showed that the region of CP comprising amino acids 116 to 206 and the region of PABP comprising amino acids 520 to 580 are involved in CP/PABP interactions. Soybean library screening with SMV NIb by yeast two-hybrid assay also identified several soybean proteins including chlorophyll a/b binding preprotein, photo-system I-N subunit, ribulose 1,5-biphosphate carboxylase, ST-LSI protein, translation initiation factor 1, TIR-NBS type R protein, RNA binding protein, ubiquitin, and LRR protein kinase. Altogether, these results suggest that potyviral replicase may comprise a multi-protein complex with PABP, CP, and other host factors.

• Parasites, Hosts and Diseases
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• v.39 no.1
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• pp.57-66
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• 2001

In the course of immunoscreening of Clonorchis sinensis cDNA library, a cDNA CsRP12 containing a tandem repeat was isolated. The cDNA CsRP 12 encodes two putative peptides of open reading frames (ORFs) 1 and 2 (CsRP12-1 and -2). The repetitive region is composed of 15 repeats of 10 amino acids. Of the two putative peptides, CsRP12-1 was proline-rich and found to have homologues in several organisms. Recombinant proteins of the putative peptides were bacterially produced and purified by an affinity chromatography Recombinant CsRP12-1 protein was recognized by sera of clonorchiasis patients and experimental rabbits, but recombinant CsRP 12-2 was not. One of the putative peptide, CsRP12-1, is designated CsPRA, proline-rich antigen of C. sinensis. Both the C-termini of CsRP12-1 and -2 were bacterially produced and analysed to show no antigenicity. Recombinant CsPRA protein showed high sensitivity and specificity. In experimental rabbits, IgG antibodies to CsPRA was produced between 4 and 8 weeks after the infection and decreased thereafter over one you. These results indicate that CsPRA is equivalent to a natural protein and a useful antigenic protein for serodiagnosis of human clonorchiasis.

• Proceedings of the Microbiological Society of Korea Conference
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• 2008.05a
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• pp.118-118
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• 2008

The phylogenetic diversity of microbial communities in calcareous mats from Spearfish Creek, a freshwater stream located in the Black Hills of South Dakota, was examined using PCR-based 16S rDNA sequence analysis. In this study, two types of calcareous mats were compared: mature mats formed on the natural substrate of rock surfaces and developing mats on an artificial substrate of glass slides. Among 63 unique isolates from a clone library of 16S rRNA genes from mature mat samples, there were 8 phyla of Bacteria represented. The predominant phylum was Proteobacteria (48%), with the $\beta$ subclass being the largest group. Denaturing gradient gel electrophoresis (DGGE) analysis of 16S rRNA genes from slide samples collected at intervals for four months showed considerable diversity of the microbial community from the earliest stages of community development. Amplicons isolated from DGGE gels and sequenced indicated that community succession has occurred without increasing microbial diversity. However, light microscopic analysis revealed a significant increase in microbial cell density throughout the community development. Scanning electron microscopy of mat samples provides evidence that diatoms are also important members of calcareous mat communities.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.371-381
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• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2A
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• pp.209-215
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• 2010

This paper describes a design of variable-length FFT/IFFT processor (VL_FCore) for OFDM-based multi-standard communication systems. The VL_FCore adopts in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate various FFT lengths in the range of $N=64{\times}2^k\;(0{\leq}k{\leq}7)$. To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The VL_FCore synthesized with a $0.35-{\mu}m$ CMOS cell library has 23,000 gates and 32 Kbytes memory, and it can operate with 75-MHz@3.3-V clock. The 64-point and 8,192-point FFT's can be computed in $2.25-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of various OFDM-based systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11C
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• pp.1029-1039
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• 2009

In this paper, the existing disparity aquisition algorithms were analyzed, on the bases of which a disparity generation technique that is superior in accuracy to the generation time was proposed. Basically it uses a pixel-by-pixel motion estimation technique. It has a merit of possibility of a high-speed operation. But the motion estimation technique has a disadvantage of lower accuracy because it depends on the similarity of the matching window regardless of the distribution characteristics of the texture in an image. Therefore, an enhanced technique to increase the accuracy of the disparity is required. This paper introduced a variable-sized window matching technique for this requirement. By the proposed technique, high accuracies could be obtained at the homogeneous regions and the object edges. A hardware to generate disparity image was designed, which was optimized to the processing speed so that a high throughput is possible. The hardware was designed by Verilog-HDL and synthesized using Hynix $0.35{\mu}m$ CMOS cell library. The designed hardware was operated stably at 120MHz using Cadence NC-VerilogTM and could process 15 frames per second at this clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8A
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• pp.785-793
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• 2007

This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.940-948
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• 2008

This paper presents a low-power, low-complexity design and implementation results of a high speed multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor is composed of the physical layer convergence procedure (PLCP) processor and physical medium dependent (PMD) processor, which have been optimized to have low-power and reduced-complexity architecture. It was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. As a result, the proposed TX-PLCP processor reduced the power consumption by as much as 81% over the bit-level operation architecture. Also, the proposed MIMO symbol detector reduced the hardware complexity by 18% over the conventional SQRD-based architecture with division circuits and square root operations.