• Journal of Microbiology and Biotechnology
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• v.23 no.8
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• pp.1047-1054
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• 2013

Witches' broom of lime is a disease caused by Candidatus Phytoplasma aurantifolia, which represents the most significant global threat to the production of lime trees (Citrus aurantifolia). Conventional disease management strategies have shown little success, and new approaches based on genetic engineering need to be considered. The expression of recombinant antibodies and fragments thereof in plant cells is a powerful approach that can be used to suppress plant pathogens. We have developed a single-chain variable fragment antibody (scFvIMP6) against the immunodominant membrane protein (IMP) of witches' broom phytoplasma and expressed it in different plant cell compartments. We isolated scFvIMP6 from a naïve scFv phage display library and expressed it in bacteria to demonstrate its binding activity against both recombinant IMP and intact phytoplasma cells. The expression of scFvIMP6 in plants was evaluated by transferring the scFvIMP6 cDNA to plant expression vectors featuring constitutive or phloem specific promoters in cassettes with or without secretion signals, therefore causing the protein to accumulate either in the cytosol or apoplast. All constructs were transiently expressed in Nicotiana benthamiana by agroinfiltration, and antibodies of the anticipated size were detected by immunoblotting. Plant-derived scFvIMP6 was purified by affinity chromatography, and specific binding to recombinant IMP was demonstrated by enzyme-linked immunosorbent assay. Our results indicate that scFvIMP6 binds with high activity and can be used for the detection of Ca. Phytoplasma aurantifolia and is also a suitable candidate for stable expression in lime trees to suppress witches' broom of lime.

• Asian Pacific Journal of Cancer Prevention
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• v.15 no.23
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• pp.10421-10425
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• 2015

Background: While the incidence of non-Hodgkins lymphoma (NHL) has been rising worldwide, the reasons remain undefined. Recent research has focused on effect of red andf processed meat intake as a risk factor, but with inconclusive results. We therefore conducted a meta-analysis of data published to date, to ascertain the overall association between intake and NHL. Materials and Methods: A published literature search was performed through Pubmed, Cochrane Library, Medline, and Science Citation Index Expanded databases for articles published in English. Pooled odds ratios (ORs) and 95% confidence intervals (95%CIs) were calculated using random or fixed effects models. Heterogeneity was assessed using Chi-square and I2 statistics. Dissemination bias was evaluated by funnel plot analysis.We performed a formal meta-analysis using summary measures from these studies. Results: In total, 11 published studies were included in the final analysis. The combined analysis revealed that there was significant association between the red meat and NHL risk (OR=1.10, 95%CI: 1.02 to 1.19, p=0.01). Additionally, there was showed significance association between processed red meat and NHL risk (OR=1.17, 95%CI: 1.06 to 1.29, p=0.001). In subgroup analysis, a statistical significant association was noted between diffuse large B-cell lymphoma (DLBCL) (OR=1.20, 95%CI: 1.04 to 2.37, P=0.01) and red meat intake. Conclusions: In this meta-Analysis, there was evidence for association between consumption of red meat, or processed meat and risk of NHL, particularly with the DLBCL subtype in the red meat case.

• Journal of Microbiology and Biotechnology
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• v.19 no.9
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• pp.911-917
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• 2009

The apoptotic caspases have been classified in accordance with their substrate specificities, as the optimal tetrapeptide recognition motifs for a variety of caspases have been determined via positional scanning substrate combinatorial library technology. Here, we focused on two proteolytic recognition motifs, DEVD and IETD, owing to their extensive use in cell death assay. Although DEVE and IETD have been generally considered to be selective for caspase-3 and -8, respectively, the proteolytic cleavage of these substrates does not display absolute specificity for a particular caspase. Thus, we attempted to monitor the cleavage preference for caspase-3, particularly using the recombinant protein substrates. For this aim, the chimeric GST:DEVD:EGFP and GST:IETD:EGFP proteins were genetically constructed by linking GST and EGFP with the linkers harboring DEVD and IETD. To our best knowledge, this work constitutes the first application for the monitoring of cleavage preference employing the recombinant protein substrates that simultaneously allow for mass and fluorescence analyses. Consequently, GST:IETD:EGFP was cleaved partially in response to caspase-3, whereas GST:DEVD:EGFP was completely proteolyzed, indicating that GST:DEVD:EGFP is a better substrate than GST:IETD:EGFP for caspase-3. Collectively, using these chimeric protein substrates, we have successfully evaluated the feasibility of the recombinant protein substrate for applicability to the monitoring of cleavage preference for caspase-3.

• The Journal of the Korea Contents Association
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• v.7 no.2
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• pp.92-99
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• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.249-254
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• 2011

This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.

• 한국태양에너지학회:학술대회논문집
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• 2008.04a
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• pp.196-202
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• 2008

Effective climate protection is a most important tasks of our time. The BIPV is one of the most interesting and promisingly possibilities of an active use of solar energy at the building. In this study it was analyzed by the case study the function of the requirement of the BIPV-module as building material and this architectural characteristic according to the kind of the module. Therefore the goal of this study is to get securing the application information of BIPV as windowpane. BIPV modules are manufactured in the form of G/G. In the case of the crystal type the Transparent and the light Transmission is to be adjusted by the spacer attitude of the cell. Although this type could not be optimal for light effect of indoors because of the inequality of shade, the moving shade play makes a dramatic Roomimage by the run of sun. The application of this type would be for canopy, window or roof in the corridor or resounds. With amorphous the type it is to be manufactured simply largely laminar, and thus that will shorten building process. There is a relatively good economy to use and to the window system easily. After the production technology is easy the transparency of the modules to adjust, and the module shows to a high degree constant characteristics of light permeability and transparency. Without mottle of module shade is good the use for the window or roof glazing of office, library, classroom, etc. to adapt. The BIPV modules took generally speaking a function as building material to the daylight use, shading, isolation and also to the sight. That means that BIPV modules have as multifunctional system to sustainable architecture good successes and they are at the same time as Design element for architecture effectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.79-84
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• 2006

This paper proposed a novel H.264 deblocking filter for low-power mobile multimedia SoCs. In H.264 deblocking filter, filtering can be skipped on some pixels when pixel value differences satisfy some specific conditions. Furthermore, whole filtering can be skipped when quantization parameter is less than 16. Based on these features, power consumption can be significantly reduced by shutting down deblocking filter partially or as a whole. The proposed deblocking filter can shut down partial or whole blocks with simple control circuits. Common hardware performs both horizontal filtering and vertical filtering. It was implemented in silicon chip using $0.35{\mu}m$ standard cell library technology. The gate count is about 20,000 gates. The maximum operation frequency is 108MHz. The maximum throughput is 30 frame/s with CCIR601 image format.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.40-47
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• 2006

The finite-field multiplication can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-parallel, bit-serial and systolic multipliers, the proposed multiplier has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.