• Proceedings of the Korean Society of Embryo Transfer Conference
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• 2002.11a
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• pp.76-76
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• 2002

본 실험은 Piezo-미세조작기(PrimeTech Ltd., Japan)를 사용하여 마우스 핵이식 후 재구축배를 CZB와 KSOM 두가지 배양액을 사용하여 체외배양성적을 비교 검토하였다. MII의 미수정란은 성숙한 4~5주령 B6D2Fl에 hCG 주사 후 14시간째에 과적 방법을 통해 난관의 팽대부로 부터 회수하였고, metaphase II chromosome-spindle complex와 최소량의 세포질을 내경이 10$\mu\textrm{m}$인 피펫으로 흡입하여 탈핵하였다. 핵이식에 사용된 난구세포(8-l0$\mu\textrm{m}$)는 3시간동안 12% PVP 에처리 하여 piezo-미세조작기를 이용하여 세포질에 세포의 핵을 직접 미세주입 하였다. 핵이식 후 생존한 재구축배는 2시간동안 배양한 후 10mM SrC1$_2$와 5$\mu\textrm{g}$/$m\ell$의 cytochalasin B가 첨가된 $Ca^{2＋}$-free CZB에서 6시간 활성화 처리하였다, 활성화 처리 후 위전핵이 관찰된 재구축란을 CZB 와 KSOM 배지에서 배양하면서 발달률을 비교하였고, 상실배 및 배반포배로 발달한 재구축배를 day 3 대리모에 이식하였다. 표 1에서 보는 바와 같이 재구축배의 2-cell로의 발달률에 있어서 KSOM이 CZB에 비하여 유의적으로 높게 나타났으며(P<0.05), 또한 4-cell과 상실배/배반 포배로의 발달률에 있어서도 KSOM이 CZB에 비하여 유의적으로 높은 발달률을 나타내었다(P<0.01). 또한 KSOM 배지에서 배양된 상실배/배반포배를 대리모에 이식한 경우에 11.5 d.p.c에 생존한 태아가 관찰되었다. 이상의 결과로 핵이식 재구축배의 활성화 처리 후의 발생에는 KSOM 배지가 CZB 배지에 비하여 유효함을 확인 할 수 있었다.그와 같은 배양 기술을 이용하여 외래유전자를 도입한 일련의 결과에 관하여 보고 하고자한다., 이것은 세포내 유전자가 transfection되지 않은 세포도 neo selection에서 선발된다는 것을 제시하고 있다. 따라서 체세포를 이용한 형질전환동물 생산을 위해서는 세포내 유전자 도입과 선발 과정에서 나타난 colony에 대하여 보다 엄격한 screen을 하는 것이 필요한 것으로 생각된다.로 우점하였다. 여름철 식물플랑크톤 대발생에 영향은 수온과 직산염이 중요하였으나, 부유물질 크게 기여하지 못하였다.애를 확인하고 지도 관점을 파악하는 것을 포함한다. 그러나 본 논문은 역사발생적 수학 학습-지도 원리의 실제적인 적용에 관하여는 기초적인 연구에 지나지 않기 때문에, 역사발생적 원리를 학교수학에 실제적으로 적용하기 위해서는 각각의 내용에 대한 철저한 역사적 분석을 바탕으로 하는 후속 연구가 필요하다./TEX>구성교육${\lrcorner}$이 조선총독부의 관리하에서 실행되었다는 것을, 당시의 사범학교를 중심으로 한 교육조직을 기술한 문헌에 의해 규명시켰다.nd of letter design which represents -natural objects and was popular at the time of Yukjo Dynasty, and there are some documents of that period left both in Japan and Korea. "Hyojedo" in Korea is supposed to have been influenced by the letter design. Asite- is also considered to have been "Japanese Letter Jobcheso." Therefore, the purpose of this study is to look into the origin of the letter designs in t

• Korean Institute of Interior Design Journal
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• v.13 no.5
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• pp.206-214
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• 2004

본 연구는 사무공간에 영향을 주는 물리적 환경 요소 (공간, 가구배치, 미, 주변요소)를 제시하고 각 환경 요소들과의 관계를 파악하며 각 물리적 환경요소들과 직업 만족도 (급여, 진급, 책무, 상사와의 관계, 물리적 공간과 배치, 수업방법의 향상, 현재 직업 만족도)와의 관계를 분석하는데 연구의 목적이 있다. 또한 물리적 환경 요소들, 직업 만족도와 개인 신상 (나이, 성별, 지위, 교육수준, 교육 경력) 의 특성들과의 상관관계를 알아보고자 한다. 본 연구는 오클라호마 주립대학교의 종신 재직권을 가진 교육대학 교수들을 대상으로 세 가지 가설을 바탕으로 작성된 설문지를 배포하여 조사되었다. 각 교수들의 사무공간은 1997년에 개보수를 마치고 그 해 여름부터 사용하고 있다. 설문은 현재 사용하고 있는 사무공간에 대한 평가, 직업 만족도에 대한 평가와 개인 신상의 특성에 대한 질문으로 조사되었다. 조사 결과 사무공간에 영향을 주는 물리적 환경 요소들 간에 밀접한 관계가 있다는 가설이 입증되었고, 또한 조사 결과 물리적 환경의 만족도가 증가할수록 직업만족도가 증가하는 것으로 물리적 사무환경에 대한 만족도와 직업에 대한 만족도가 직접적인 관계가 있다는 가설 또한 확증되었다. 물리적 환경요소, 직업 만족도와 개인 신상의 특성들과의 상관관계가 있다는 가설은 전체적으로는 입증되지는 않았지만 부분적으로 요소들 간에 관계를 보여주고 있다. 남성이 여성보다 가구배치에 대해 불만족스러웠고 교육경력이 적을수록 사무공간의 냉난방과 환기에 대한 불만족을 보였다. 본 연구의 결과는 교수들의 사무환경의 부정적, 긍정적 견해를 지각하여 사무 환경의 질을 높이는데 도움이 되는데 중요한 역할을 할 수 있겠다. 본 연구는 교육대학의 교수들에 국한되어 있었던 바 추후에는 전체 교육자들을 대상으로 장기간의 관찰을 통한 연구가 요구되어 진다.신만의 고유한 해결책으로 발전시키는지를 고찰하고자 한다. 본 논문의 목적은 서울을 사례분석 중 하나로 사용하여 인테리어 디자인 분야의 경계를 대도시로 확장하는 동시에 새로운 적용영역의 가능성을 탐구하는데 있다 하겠다.[C/N]의 값을 나타내었다.다.다.화 기술, 구동방법등에 대한 기술개요와 국내외 기술동향에 대하여 소개하고자 한다.었다.다._{2}$가 0.25[wt%] 첨가된 시편의 20[.deg.C]에서의 유전상수는 16,700으로 최대값을 유전손실을 1.28[%]로 최소값을 나타내었다. 또한 모든 시편은 온도 및 주파수에 따라 유전상수가 완만하게 변화하는 유전이완 특성을 나타내었다.다.수적인 물의 양에 따른 DIAION WA30의 라세미화 효율에 관하여 실험한 결과, 물의 양이 증가할수록 그 효율은 감소하였다. DIAION WA30을 라세미화 촉매로 사용하여 아이소옥탄 내에서 라세믹 나프록센 2,2,2-트리플로로에틸 씨오에스터의 효소적 DKR 반응을 수행해 보았다. 그 결과 DIAION WA30을 사용하지 않은 경우에 비해 반응 전환율과 생성물의 광학 순도는 급격히 향상되었다. 전통적 광학분할 반응의 최대 50%라는 전환율의 제한이 본 연구에서 찾은 DIAION WA30을 첨가함으로써 성공적으로 극복되었다. 또한 고체 염기촉매인 DIAION WA30의 사용은 라세미화 촉매의 회수 및 재사용이 가능하게 해준다.해준다.다. TN5 세포주를 0.2 L 규모 (1 L spinner flask)oJl에서 세포간의 응집현상 없이 부유배양에 적응,배양시킨 후 세포성장 시기에 따른 발현을 조사한 결과 1 MOI의 감염조건 하에서는 $0.6\times10^6$cell/mL의 early exponential시기의 세포밀도에서 72시간 배양하였을 대 최대 발현양을 나타내었다. 나타내었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Journal of Food Hygiene and Safety
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• v.28 no.2
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• pp.188-193
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• 2013

Anatoxin-a, saxitoxin and neosaxitoxin are produced by Aphanizomenon flos-aquae that is a sort of the cyanobacteria phylum. Therefore, it is not permitted for food materials in Korea. Traditionally, the classification of cyanobacteria has been based on morphological characters such as trichome width, cell size, division planes, shape, and the presence of character such as gas vacuole. But, some diagnostic features, such as gas vacuole or akinetes, can show variation with different environmental or growth conditions and even be lost during cultivation. Therefore, we developed detection method for functional foods containing Aph. flos-aquae by PCR. To design the primer, 16S rRNA region of Aph. flos-aquae, Spirulina laxissima, and Spirulina spp. registered in the GeneBank (www.ncbi.nlm.nih.gov) have been used and for comparative analysis, BioEdit ver. 7.0.9.0. was used. As a result, we was design AFA-F1/AFA-R1 (363 bp) primer for the differentiation Aph. flos-aquae from chlorella, spirulina, green tea, and spinach. Also, it could be distinguished chlorella and spirulina products those are made to contain 1% Aph. flos-aquae.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• Journal of the Korean Institute of Gas
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• v.20 no.4
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• pp.78-84
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• 2016

In this work, finite element investigations were carried out to optimize reverse drawing process design for manufacture of high-capacity aluminum liner used in fuel cell vehicle. The tensile tests with aluminum alloy Al6061 annealed at $350^{\circ}C$ were carried out to obtain the flow stresses. In order to estimate more accurate flow stresses after necking, the flow stresses were estimated from the comparison of load vs. displacement curves which were obtained from experimental and simulation results of tensile tests. In case of finite element analyses of reverse drawing processes, it was focused on the effects of process designs such as punch and die designs, blank holding force, drawing ratio and the clearance between the punch and blank holder on the generation of wrinkle and fracture of the blank and partially heated punch. However, it was revealed that experimental results still show the fracture at the end of 2nd drawn cup, although partially heated punch is used. Nevertheless, the drawn cup can be used because the sufficient length of the drawn cup for the next flow forming process and spinning process was obtained.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• Journal of Korean Tunnelling and Underground Space Association
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• v.19 no.2
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• pp.143-159
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• 2017

A probabilistic fragility assessment procedure is developed in this paper to predict risks of damage arising from seismic loading to the two-cell RC box tunnel. Especially, the paper focuses on establishing a simplified methodology to derive fragility curves which are an indispensable ingredient of seismic fragility assessment. In consideration of soil-structure interaction (SSI) effect, the ground response acceleration method for buried structure (GRAMBS) is used in the proposed approach to estimate the dynamic response behavior of the structures. In addition, the damage states of tunnels are identified by conducting the pushover analyses and Latin Hypercube sampling (LHS) technique is employed to consider the uncertainties associated with design variables. To illustrate the concepts described, a numerical analysis is conducted and fragility curves are developed for a large set of artificially generated ground motions satisfying a design spectrum. The seismic fragility curves are represented by two-parameter lognormal distribution function and its two parameters, namely the median and log-standard deviation, are estimated using the maximum likelihood estimates (MLE) method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.178-184
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• 2015

This paper proposes a hardware architecture for high performance Deblocking filter(DBF) in High Efficiency Video Coding for UHD(Ultra High Definition) videos. This proposed hardware architecture which has less processing time has a 4-stage pipelined architecture with two filters and parallel boundary strength module. Also, the proposed filter can be used in low-voltage design by using clock gating architecture in 4-stage pipeline. The segmented memory architecture solves the hazard issue that arises when single port SRAM is accessed. The proposed order of filtering shortens the delay time that arises when storing data into the single port SRAM at the pre-processing stage. The DBF hardware proposed in this paper was designed with Verilog HDL, and was implemented with 22k logic gates as a result of synthesis using TSMC 0.18um CMOS standard cell library. Furthermore, the dynamic frequency can process UHD 8k($7680{\times}4320$) samples@60fps using a frequency of 150MHz with an 8K resolution and maximum dynamic frequency is 285MHz. Result from analysis shows that the proposed DBF hardware architecture operation cycle for one process coding unit has improved by 32% over the previous one.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.4
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• pp.372-381
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• 2001

In this paper SEED, the Korea Standard 128-bit block cipher algorithm is implemented with VHDL and mapped into one FPGA. SEED consists of round key generation block, F function block, G function block, round processing block, control block and I/O block. The designed SEED is realized in an FPGA but we design it technology-independently so that ASIC or core-based implementation is possible. SEED requires many hardware resources which may be impossible to realize in one FPGA. So it is necessary to minimize hardware resources. In this paper only one G function is implemented and is used for both the F function block and the round key block. That is, by using one G function sequentially, we can realize all the SEED components in one FPGA. The used cell rate after synthesis is 80% in Altem FLEXI0KlOO. The resulted design has 28Mhz clock speed and 14.9Mbps performance. The SEED hardware is technology-independent and no other external component is needed. Thus, it can be applied to other SEED implementations and cipher systems which use SEED.